MEMORY SYSTEM AND METHOD HAVING POINT-TO-POINT LINK
First Claim
1. A memory system, comprising:
- a controller for generating a control signal; and
a memory module, the memory module comprising;
a primary memory, directly coupled to the controller external to the memory module, for receiving the control signal from the controller using a first signal transfer protocol; and
a secondary memory coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory using a second signal transfer protocol, and communicating with the controller through the primary memory;
wherein the second signal transfer protocol is an at least partially serialized version of the first signal transfer protocol.
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Abstract
A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.
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Citations
12 Claims
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1. A memory system, comprising:
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a controller for generating a control signal; and a memory module, the memory module comprising; a primary memory, directly coupled to the controller external to the memory module, for receiving the control signal from the controller using a first signal transfer protocol; and a secondary memory coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory using a second signal transfer protocol, and communicating with the controller through the primary memory; wherein the second signal transfer protocol is an at least partially serialized version of the first signal transfer protocol. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification