System and Method for Monitoring and Repairing Memory

• US 20110289349A1
• Filed: 05/24/2010
• Published: 11/24/2011
• Est. Priority Date: 05/24/2010
• Status: Abandoned Application

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Singletary, Daniel V., Loeser, Matthias J., Joshi, Sanjeev A., Nazar, Shadab
• Application Number:
  US12/785,812
• Publication Number:
  US 20110289349A1
• Time in Patent Office: Days
• US Class Current: 714/6.24
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

Monitoring and repairing memory includes selecting a first memory bank comprising a plurality of memory cells to analyze. The plurality of memory cells are copied from the first memory bank to a second memory bank, wherein a request to access the first memory bank is redirected to the second memory bank. A determination is made whether the first memory bank comprises an error of the memory cell.

Claims

1. A method for monitoring and repairing memory, comprising:

selecting a first memory bank comprising a plurality of memory cells to analyze;

copying the plurality of memory cells from the first memory bank to a second memory bank, wherein a request to access the first memory bank is redirected to the second memory bank; and

determining whether the first memory bank comprises an error of the memory cell.

2. The method of claim 1, further comprising:

receiving a request to access the first memory bank;

continuing the copying of the plurality of memory cells;

accessing the second memory bank to fulfill the request.

3. The method of claim 1, further comprising:

designating the second memory bank as a primary memory bank; and

designating the first memory bank as a spare memory bank.

4. The method of claim 1, further comprising:

identifying an error associated with a memory cell;

determining that the identified memory cell error is a transient error;

storing a location associated with the transient error in a database; and

analyzing the stored transient error location to identify a recurring error.

5. The method of claim 4, wherein the transient error is associated with one or more Error Correcting Codes (ECCs).

6. The method of claim 1, further comprising:

identifying an error associated with a memory cell;

determining that the memory cell error is repairable; and

repairing the memory cell error by activating one or more redundant circuit elements associated with the first memory bank.

7. The method of claim 1, further comprising:

identifying an error associated with a memory cell;

storing a location associated with the identified memory cell error in a memory table to repair the identified memory cell error; and

redirecting a request to access the identified location to an alternate memory location associated with the memory table.

8. The method of claim 1, further comprising:

determining that the first memory bank comprises a plurality of memory cell errors;

determining if the plurality of memory cell errors has reached a predetermined limit; and

designating the first memory bank as out-of-service if the pre-determined limit has been reached.

9. A non-transitory computer readable medium comprising logic, the logic, when executed by a processor, operable to:

select a first memory bank comprising a plurality of memory cells to analyze;

copy the plurality of memory cells from the first memory bank to a second memory bank, wherein a request to access the first memory bank is redirected to the second memory bank; and

determine whether the first memory bank comprises an error of the memory cell.

10. The medium of claim 9, further operable to:

receive a request to access the first memory bank;

continue the copying of the plurality of memory cells; and

access the second memory bank to fulfill the request.

11. The medium of claim 9, further operable to:

designate the second memory bank as a primary memory bank; and

designate the first memory bank as a spare memory bank.

12. The medium of claim 9, further operable to:

identify an error associated with a memory cell;

determine that the identified memory cell error is a transient error;

store a location associated with the transient error in a database; and

analyze the stored transient error location to identify a recurring error.

13. The medium of claim 12, further operable to, wherein the transient error is associated with one or more Error Correcting Codes (ECCs).

14. The medium of claim 9, further operable to:

identify an error associated with a memory cell;

determine that the memory cell error is repairable; and

repair the memory cell error by activating one or more redundant circuit elements associated with the first memory bank.

15. The medium of claim 9, further operable to:

identify an error associated with a memory cell;

store a location associated with the identified memory cell error in a memory table to repair the identified memory cell error; and

redirect a request to access the identified location to an alternate memory location associated with the memory table.

16. The medium of claim 9, further operable to:

determine that the first memory bank comprises a plurality of memory cell errors;

determine if the plurality of memory cell errors has reached a predetermined limit; and

designate the first memory bank as out-of-service if the pre-determined limit has been reached.

17. An apparatus for monitoring and repairing memory, comprising:

a first memory bank comprising a plurality of memory cells;

a monitor module comprising a processor component and operable to;

select the first memory bank to analyze;

copy the plurality of memory cells from the first memory bank to a second memory bank, wherein a request to access the first memory bank is redirected to the second memory bank; and

a test module comprising a second processor component and operable to;

determine whether the first memory bank comprises an error of the memory cell.

18. The apparatus of claim 17, wherein the monitor module is further operable to:

receive a request to access the first memory bank;

continue the copying of the plurality of memory cells; and

access the second memory bank to fulfill the request.

19. The apparatus of claim 17, wherein the monitor module is further operable to:

designate the second memory bank as a primary memory bank; and

designate the first memory bank as a spare memory bank.

20. The apparatus of claim 17, further comprising a repair module comprising a third processor component and further operable to:

identify an error associated with a memory cell;

determine that the identified memory cell error is a transient error;

store a location associated with the transient error in a database; and

analyze the stored transient error location to identify a recurring error.