METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE

• US 20110289380A1
• Filed: 05/21/2010
• Published: 11/24/2011
• Est. Priority Date: 05/21/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: WILKERSON, CHRISTOPHER B., Wu, Wei, Chishti, Zeshan A., Lu, Shih-Lien, Alameldeen, Alaa R., Somasekhar, Dinesh
• Granted Patent: US 8,640,005 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories

Abstract

A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.

Claims

1. An apparatus comprising:

a cache memory; and

an error correction logic to receive data stored in a cache line in the cache memory, the error correction logic comprising;

a first error correction logic to generate a syndrome for the received cache line read from the cache memory to determine a number of errors in the cache line; and

a second error correction logic to receive the cache line from the first error correction logic only if the cache line has greater than one error, the second error correction logic to perform multi-bit error correction for the received cache line.

2. The apparatus of claim 1, further comprising:

repair logic, the repair logic to fix known errors in the cache line prior to forwarding the cache line to the error correction logic.

3. The apparatus of claim 1, wherein the cache memory is volatile memory.

4. The apparatus of claim 1, wherein the first error correction logic includes a decoder to perform correction in a shorter period of time than the multi-bit error correction.

5. The apparatus of claim 1, wherein the first error correction logic includes syndrome generation logic and error correction logic for cache lines with zero or one failures.

6. The apparatus of claim 1, further comprising:

a Recently Accessed Line Table (RALT) coupled to the address bus of the cache memory, the RALT to determine if the addressed cache line has been accessed within a current refresh time period of the volatile cache memory.

7. The apparatus of claim 6, wherein the RALT is used to track recently accessed lines.

8. The apparatus of claim 1, wherein the first error correction logic to perform error correction for the single error in the received cache line.

9. A method comprising:

storing data in a cache memory;

receiving, by an error correction logic data stored in a cache line in the cache memory, the error correction logic comprising a first error correction logic and a second error correction logic;

generating, by the first error correction logic, a syndrome for the received cache line read from the cache memory to determine a number of errors in the cache line;

forwarding the cache line, by the first error correction logic to a second error correction logic only if the cache line has greater than one error; and

performing, by the second error correction logic, multi-bit error correction for the received cache line.

10. The method of claim 9, further comprising:

repairing, by repair logic, known errors in the cache line prior to forwarding the cache line to the error correction logic.

11. The method of claim 9, further comprising:

performing, by the first error correction logic, correction in a shorter period of time than the multi-bit error correction.

12. The method of claim 11, further comprising:

determining, by a Recently Accessed Line Table (RALT) coupled to the address bus of the cache memory, if the addressed cache line has been accessed within a current refresh time period of the cache memory.

13. The method of claim 12, further comprising:

tracking, by the RALT, recently accessed cache lines.

14. The method of claim 9, further comprising:

performing, by the first error correction logic, error correction for the single error in the received cache line.

15. An article including a machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:

storing data in a cache memory;

receiving, by an error correction logic data stored in a cache line in the cache memory, the error correction logic comprising a first error correction logic and a second error correction logic;

generating, by the first error correction logic, a syndrome for the received cache line read from the cache memory to determine a number of errors in the cache line;

forwarding the cache line, by the first error correction logic to a second error correction logic only if the cache line has greater than one error; and

performing, by the second error correction logic, multi-bit error correction for the received cache line.

16. The article of claim 15 further comprising:

repairing, by repair logic, known errors in the cache line prior to forwarding the cache line to the error correction logic.

17. The article of claim 15, further comprising:

performing, by the first error correction logic, correction in a shorter period of time than the multi-bit error correction.

18. The article of claim 15, further comprising:

determining, by a Recently Accessed Line Table (RALT) coupled to the address bus of the cache memory, if the addressed cache line has been accessed within a current refresh time period of the cache memory.

19. The article of claim 15, further comprising:

performing, by the first error correction logic, error correction for the single error in the received cache line.

20. A system comprising:

an external memory; and

a processor, the processor comprising;

a cache memory to store data read from the external memory; and

an error correction logic to receive data stored in a cache line in the cache memory, the error correction logic comprising;

a first error correction logic to generate a syndrome for the received cache line read from the cache memory to determine a number of errors in the cache line; and

a second error correction logic to receive the cache line from the first error correction logic only if the cache line has greater than one error, the second error correction logic to perform multi-bit error correction for the received cache line.

21. The system of claim 20, further comprising:

repair logic, the repair logic to fix known errors in the cache line prior to forwarding the cache line to the error correction logic.

22. The system of claim 20, wherein the first error correction logic includes a decoder to perform correction in a shorter period of time than the multi-bit error correction and syndrome generation logic and error correction logic for cache lines with zero or one failures.