SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD OF MAKING THE SAME

• US 20110291234A1
• Filed: 07/30/2010
• Published: 12/01/2011
• Est. Priority Date: 05/27/2010
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Granted Patent: US 8,455,978 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A semiconductor circuit structure includes an interconnect region, and a material transfer region. The semiconductor circuit structure includes a conductive bonding region which couples the material transfer region to the interconnect region through a bonding interface. The conductive bonding region includes a barrier layer between a conductive layer and bonding layer. The bonding layer is positioned towards the material transfer region, and the conductive layer is positioned towards the interconnect region.

Claims

1. A semiconductor structure, comprising:

an interconnect region;

a material transfer region; and

a conductive bonding region which couples the material transfer region to the interconnect region through a bonding interface,

wherein the conductive bonding region includes a conductive layer and barrier layer.

2. The structure of claim 1, wherein the conductive layer is thicker than the barrier layer.

3. The structure of claim 1, wherein the conductive layer is more conductive than the barrier layer.

4. The structure of claim 1, wherein the barrier layer is more resistive than the conductive layer.

5. The structure of claim 1, wherein the barrier layer extends between the conductive layer and material transfer region.

6. The structure of claim 1, wherein the bonding interface is a metal-semiconductor bonding interface.

7. The structure of claim 1, wherein the interconnect region includes a conductive line which extends through a dielectric material.

8. The structure of claim 7, wherein the conductive line is connected to the conductive bonding region.

9. The structure of claim 7, wherein the conductive line is in communication with the barrier layer through the conductive layer.

10. The structure of claim 1, wherein the conductive bonding region includes a bonding layer.

11. The structure of claim 10, wherein the conductive layer is thicker than the bonding layer.

12. The structure of claim 10, wherein the bonding layer is thicker than the barrier layer.

13. The structure of claim 10, wherein the bonding layer is more conductive than the barrier layer.

14. The structure of claim 10, wherein the bonding layer extends between the barrier layer and material transfer region.

15. The structure of claim 10, wherein the bonding interface is a metal-semiconductor bonding interface.

16. The structure of claim 10, wherein the interconnect region includes a conductive line which extends through a dielectric material.

17. The structure of claim 16, wherein the conductive line is in communication with the bonding layer.

18. The structure of claim 16, wherein the conductive line is in communication with the bonding layer through the conductive layer.

19. The structure of claim 1, wherein the material transfer region includes a dielectric material region.

20. The structure of claim 1, wherein the material transfer region includes a semiconductor material region.

21. The structure of claim 1, wherein the material transfer region includes a single crystalline semiconductor material region.

22. The structure of claim 1, wherein the material transfer region includes a stack of single crystalline semiconductor material layers.

23. A semiconductor structure, comprising:

a support substrate which carries an electronic device;

an interconnect region carried by the support substrate, the interconnect region including a conductive line in communication with the electronic device;

a conductive bonding region in communication with the conductive line, wherein the conductive bonding region includes a conductive layer and bonding layer; and

a material transfer region coupled to the interconnect region through the conductive bonding region.

24. The structure of claim 23, wherein the conductive layer is thicker than the bonding layer.

25. The structure of claim 23, wherein the conductive layer is less resistive than the bonding layer.

26. The structure of claim 23, wherein the conductive layer is more conductive than the bonding layer.

27. The structure of claim 23, wherein the bonding layer extends between the conductive layer and material transfer region.

28. The structure of claim 23, wherein the conductive bonding region establishes a bonding interface between the interconnect region and material transfer region.

29. The structure of claim 28, wherein the bonding interface is a metal-semiconductor bonding interface.

30. The structure of claim 23, wherein the interconnect region includes a conductive line which extends through a dielectric material.

31. The structure of claim 30, wherein the conductive line is connected to the conductive bonding region.

32. The structure of claim 30, wherein the conductive line is in communication with the bonding layer through the conductive layer.

33. The structure of claim 23, wherein the conductive bonding region includes a barrier layer.

34. The structure of claim 33, wherein the conductive layer is thicker than the barrier layer.

35. The structure of claim 33, wherein the bonding layer is thicker than the barrier layer.

36. The structure of claim 33, wherein the bonding layer is more conductive than the barrier layer.

37. The structure of claim 33, wherein the bonding layer extends between the barrier layer and material transfer region.

38. The structure of claim 37, wherein the bonding layer establishes a metal-semiconductor bonding interface with the material transfer region.

39. The structure of claim 33, wherein the interconnect region includes a conductive line which extends through a dielectric material.

40. The structure of claim 39, wherein the conductive line is in communication with the bonding layer.

41. The structure of claim 39, wherein the conductive line is in communication with the barrier layer through the conductive layer.

42. A method of forming a semiconductor structure, comprising:

coupling a material transfer region to an interconnect region through a bonding interface established with a conductive bonding region,

wherein the conductive bonding region includes a conductive layer and barrier layer.

43. The method of claim 42, further including forming the conductive bonding region so the conductive layer is thicker than the barrier layer.

44. The method of claim 42, further including forming the conductive bonding region so the conductive layer is more conductive than the barrier layer.

45. The method of claim 42, further including forming the conductive bonding region so the barrier layer is more resistive than the conductive layer.

46. The method of claim 42, further including forming the conductive bonding region so the barrier layer extends between the conductive layer and material transfer region.

47. The method of claim 42, wherein the bonding interface is a metal-semiconductor bonding interface.

48. The method of claim 42, further including forming the interconnect region by forming a conductive line which extends through a dielectric material region.

49. The method of claim 48, further including forming the conductive bonding region so it is in communication with the conductive line.

50. The method of claim 48, further including forming the barrier layer so it is in communication with the conductive line through the conductive layer.

51. The method of claim 42, further including forming the conductive bonding region so it includes a bonding layer.

52. The structure of claim 51, further including forming the conductive layer so it is thicker than the bonding layer.

53. The method of claim 51, further including forming the bonding layer so it is thicker than the barrier layer.

54. The method of claim 51, further including forming the bonding layer so it is more conductive than the barrier layer.

55. The method of claim 51, further including forming the bonding layer so it extends between the barrier layer and material transfer region.

56. The method of claim 51, wherein the bonding interface is a metal-semiconductor bonding interface.

57. The method of claim 51, further including forming the interconnect region by forming a conductive line which extends through a dielectric material region.

58. The method of claim 57, further including forming the conductive line so it is in communication with the bonding layer.

59. The method of claim 57, further including forming the conductive line so it is in communication with the bonding layer through the conductive layer.

60. A method of forming a semiconductor structure, comprising:

forming a support substrate which carries an electronic device;

forming an interconnect region carried by the support substrate, the interconnect region including a conductive line in communication with the electronic device;

forming a conductive bonding region in communication with the conductive line, wherein the conductive bonding region includes a conductive layer and bonding layer; and

coupling a material transfer region to the interconnect region through the conductive bonding region.

61. The method of claim 60, further including forming the conductive layer so it is thicker than the bonding layer.

62. The method of claim 60, further including forming the conductive layer so it is less resistive than the bonding layer.

63. The method of claim 60, further including forming the conductive layer so it is more conductive than the bonding layer.

64. The method of claim 60, further including forming the bonding layer so it extends between the conductive layer and material transfer region.

65. The method of claim 60, further including forming the conductive bonding region so it establishes a bonding interface between the interconnect region and material transfer region.

66. The method of claim 65, wherein the bonding interface is a metal-semiconductor bonding interface.

67. The method of claim 60, further including forming the interconnect region by forming a conductive line which extends through a dielectric material region.

68. The method of claim 67, further including forming the conductive bonding region so it is in communication with the conductive line.

69. The method of claim 67, further including forming the bonding layer so it is in communication with the conductive line through the conductive layer.

70. The method of claim 60, further including forming a barrier layer with the conductive bonding region.

71. The method of claim 70, further including forming the conductive layer so it is thicker than the barrier layer.

72. The method of claim 70, further including forming the bonding layer so it is thicker than the barrier layer.

73. The method of claim 70, further including forming the bonding layer so it is more conductive than the barrier layer.

74. The method of claim 70, further including forming the bonding layer so it extends between the barrier layer and material transfer region.

75. The method of claim 70, wherein the bonding interface is a metal-semiconductor bonding interface.

76. The method of claim 70, further including forming the interconnect region by forming a conductive line which extends through a dielectric material region.

77. The method of claim 76, further including forming the bonding layer so it is in communication with the conductive line.

78. The method of claim 76, further including forming the bonding layer so it is in communication with the conductive line through the barrier layer.

79. The method of claim 64, wherein forming the material transfer region includes forming a dielectric material region.

80. The method of claim 64, wherein forming the material transfer region includes forming a semiconductor material region.

81. The method of claim 64, wherein forming the material transfer region includes forming a single crystalline semiconductor material region.

82. The method of claim 64, wherein forming the material transfer region includes forming a stack of single crystalline semiconductor material.

83. A semiconductor structure, comprising:

a conductive bonding region;

a semiconductor material region coupled to the conductive bonding region through a bonding interface; and

a capacitor in communication with the semiconductor material region.

84. The structure of claim 83, wherein the bonding interface is established in response to coupling the semiconductor material region to the conductive bonding region.

85. The structure of claim 83, wherein the bonding interface is a metal-to-metal bonding interface.

86. The structure of claim 83, wherein the semiconductor material region extends between the conductive bonding region and capacitor.

87. The structure of claim 83, wherein the semiconductor material region includes a base support structure.

88. The structure of claim 83, wherein the semiconductor material region includes crystalline semiconductor material.

89. The structure of claim 83, wherein the semiconductor material region includes single crystalline semiconductor material.

90. The structure of claim 83, wherein the capacitor stores a charge in response to a signal flowing through the bonding interface.

91. The structure of claim 83, further including a control dielectric which extends around the semiconductor material region.

92. The structure of claim 91, further including a control terminal which extends around the control dielectric.

93. The structure of claim 92, wherein the conductivity of the semiconductor material region is adjustable in response to adjusting a signal provided to the control terminal.

94. The structure of claim 93, wherein a charge of the capacitor is adjustable in response to adjusting the conductivity of the semiconductor material region.

95. The structure of claim 83, further including a mesa structure which includes the semiconductor material region.

96. The structure of claim 95, further including a control dielectric which extends annularly around the mesa structure.

97. The structure of claim 95, further including a control terminal which extends annularly around the mesa structure.

98. The structure of claim 97, wherein the conductivity of the mesa structure is adjustable in response to adjusting a signal provided to the control terminal.

99. The structure of claim 97, wherein a current flow through the bonding interface is adjustable in response to adjusting a signal provided to the control terminal.

100. The structure of claim 97, wherein the operation of the capacitor is controllable in response to a signal provided to the control terminal.

101. The structure of claim 95, wherein the bonding interface is established in response to coupling the semiconductor material region to the conductive bonding region.

102. The structure of claim 95, wherein the bonding interface is a metal-to-metal bonding interface.

103. The structure of claim 95, wherein the mesa structure extends between the conductive bonding region and capacitor.

104. The structure of claim 95, wherein the mesa structure includes crystalline semiconductor material.

105. The structure of claim 95, wherein the mesa structure includes single crystalline semiconductor material.

106. The structure of claim 95, wherein the capacitor stores a charge in response to a signal flowing through the bonding interface and mesa structure.

107. The structure of claim 95, wherein the semiconductor material region includes a base support structure which carries the mesa structure.

108. The structure of claim 107, further including a control dielectric which extends around the mesa structure.

109. The structure of claim 108, further including a control terminal which extends around the control dielectric.

110. The structure of claim 109, wherein the conductivity of the mesa structure is adjustable in response to adjusting a signal provided to the control terminal.

111. The structure of claim 109, wherein a charge of the capacitor is adjustable in response to adjusting the conductivity of the mesa structure.