PLANARIZING ETCH HARDMASK TO INCREASE PATTERN DENSITY AND ASPECT RATIO

• US 20110291243A1
• Filed: 05/28/2010
• Published: 12/01/2011
• Est. Priority Date: 05/28/2010
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Reilly, Patrick, Rathi, Sudha, Seamons, Martin Jay, Chan, Chiu, Lee, Kwangduk Douglas
• Granted Patent: US 8,513,129 B2
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

Methods for manufacturing a semiconductor device in a processing chamber are provided. In one embodiment, a method includes depositing over a substrate a first base material having a first set of interconnect features, filling an upper portion of the first set of interconnect features with an ashable material to an extent capable of protecting the first set of interconnect features from subsequent processes while being easily removable when desired, planarizing an upper surface of the first base material such that an upper surface of the ashable material filled in the first set of interconnect features is at the same level with the upper surface of the first base material, providing a substantial planar outer surface of the first base material, depositing a first film stack comprising a second base material on the substantial planar outer surface of the first base material, forming a second set of interconnect features in the second base material, wherein the second set of interconnect features are aligned with the first set of interconnect features, and removing the ashable material from the first base material, thereby extending a feature depth of the semiconductor device by connecting the second set of interconnect features to the first set of interconnect features. In another embodiment, a method includes providing a base material having a first film stack deposited thereon, wherein the base material is formed over the substrate and having a first set of interconnect features filled with an amorphous carbon material, the first film stack comprising a first amorphous carbon layer deposited on a surface of the base material, a first anti-reflective coating layer deposited on the first amorphous carbon layer, and a first photoresist layer deposited on the first anti-reflective coating layer, and patterning a portion of the first photoresist layer by shifting laterally a projection of a mask on the first photoresist layer relative to the substrate a desired distance, thereby introducing into the first photoresist layer a first feature pattern to be transferred to the underlying base material, wherein the first feature pattern is not aligned with the first set of interconnect features.

Claims

1. A method for manufacturing a semiconductor device in a processing chamber, comprising:

depositing over a substrate a first base material having a first set of interconnect features;

filling an upper portion of the first set of interconnect features with an ashable material;

planarizing an upper surface of the first base material such that an upper surface of the ashable material filled in the first set of interconnect features is at the same level with the upper surface of the first base material, the upper surface of the ashable material and the first base material provide a substantial planar outer surface;

depositing a film stack comprising a second base material on the substantial planar outer surface;

forming a second set of interconnect features in the second base material, wherein the second set of interconnect features are aligned with the first set of interconnect features; and

removing the ashable material from the first base material to extend a feature depth of the semiconductor device by connecting the second set of interconnect features to the first set of interconnect features.

4. The method of claim 1, wherein the film stack further comprises:

a hardmask layer deposited on the second base material;

an anti-reflective coating layer deposited on the hardmask layer; and

a photoresist layer deposited on the anti-reflective coating layer.

5. The method of claim 1, wherein each of the first and second base materials comprises a plurality of alternating oxide and nitride materials, one or more oxide materials or nitride materials, polysilicon or amorphous silicon materials, oxides alternating with amorphous silicon, oxides alternating with polysilicon, undoped silicon alternating with doped silicon, undoped polysilicon alternating with doped polysilicon, updoped amorphous silicon alternating with doped amorphous silicon.

6. The method of claim 1, wherein each of the first and second sets of interconnect features comprises two or more contact openings arranged in parallel to one another.

26. The method of claim 4, wherein the hardmask layer comprises doped or undoped amorphous carbon, silicon oxide, or polysilicon material.

2-3. -3. (canceled)

7. A method for manufacturing a semiconductor device in a processing chamber, comprising:

depositing over a substrate a first base material having a first set of interconnect features formed therein;

filling an upper portion of the first set of interconnect features with an ashable material to

provide a substantial planar outer surface of the first base material;

depositing a second base material on the substantial planar outer surface of the first base material;

forming a second set of interconnect features in the second base material to expose the ashable material filled in the upper portion of the first set of interconnect features, wherein the second set of interconnect features is aligned with the first set of interconnect features; and

removing the ashable material filled in the upper portion of the first set of interconnect features so that the second set of interconnect features connects to the first set of interconnect features.

11. The method of claim 7, wherein the first set of interconnect features comprises two or more contact openings arranged in parallel to one another.

16. The method of claim 7, wherein each of the first and second base materials comprises a plurality of alternating oxide and nitride materials, one or more oxide or nitride materials, polysilicon or amorphous silicon materials, oxides alternating with amorphous silicon, oxides alternating with polysilicon, undoped silicon alternating with doped silicon, undoped polysilicon alternating with doped polysilicon, updoped amorphous silicon alternating with doped amorphous silicon.

17. The method of claim 7, wherein the ashable material comprises hydrocarbon-containing organic materials, graphite carbon materials, diamond carbon materials, diamond-like carbon materials, amorphous carbon materials, or the like.

8-10. -10. (canceled)

12-15. -15. (canceled)

18-19. -19. (canceled)

20. A method for processing a substrate in a processing chamber, comprising:

providing a base material having a film stack deposited thereon, wherein the base material is formed over the substrate and having a first set of interconnect features formed therein, the film stack comprising;

a hardmask layer contacting an upper surface of the base material;

an anti-reflective coating layer deposited on the hardmask layer; and

a photoresist layer deposited on the anti-reflective coating layer; and

patterning the film stack to introduce into the hardmask layer a feature pattern to be transferred to the underlying base material, wherein the feature pattern is not aligned with the first set of interconnect features.

21. The method of claim 20, further comprising:

transferring the feature pattern from the hardmask layer to the base material to form

a second set of interconnect features in the base material, wherein the first and second sets of interconnect features have substantially identical feature size being arranged in parallel and equally spaced from each other in a given region; and

removing the hardmask layer and any remaining materials from the first and second sets of interconnect features.

22. The method of claim 20, wherein the base material comprises a plurality of alternating oxide and nitride materials, oxides alternating with amorphous silicon, oxides alternating with polysilicon, undoped silicon alternating with doped silicon, undoped polysilicon alternating with doped polysilicon, or updoped amorphous silicon alternating with doped amorphous silicon.

27. The method of claim 20, further comprising:

filling an upper portion of the first set of interconnect features with an ashable material; and

planarizing the upper surface of the first base material such that an upper surface of the ashable material filled in the first set of interconnect features is at the same level with the upper surface of the first base material.

28. The method of claim 20, wherein patterning the film stack comprises:

shifting laterally a projection of a mask on the photoresist layer relative to the substrate a predetermined distance to introduce the feature pattern into the photoresist layer.

29. The method of claim 20, wherein the base material comprises one or more oxide or nitride materials, aluminum, tungsten, or copper materials, polysilicon or amorphous silicon materials.

30. The method of claim 22, wherein the substrate comprise crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitrides, doped silicon, germanium, gallium arsenide, glass, sapphire, or the like.

23. (canceled)

24. A semiconductor device, comprising:

a substrate having a base material deposited thereon, wherein the base material has a set of interconnect features in which an upper portion of the set of interconnect features is filled with an ashable material;

a patterned amorphous carbon layer formed on the base material, the patterned amorphous carbon layer has a first feature pattern being aligned with the set of interconnect features; and

a patterned anti-reflective coating layer formed on the patterned amorphous carbon layer, the patterned anti-reflective coating layer has a second feature pattern being aligned with the set of interconnect features.

25. The semiconductor device of claim 24, wherein the base material comprises a plurality of alternating oxide and nitride materials, one or more oxide or nitride materials, polysilicon or amorphous silicon materials, oxides alternating with amorphous silicon, oxides alternating with polysilicon, undoped silicon alternating with doped silicon, undoped polysilicon alternating with doped polysilicon, updoped amorphous silicon alternating with doped amorphous silicon.

31. The method of claim 24, wherein the ashable material comprises hydrocarbon-containing organic materials, graphite carbon materials, diamond carbon materials, diamond-like carbon materials, amorphous carbon materials, or the like.