SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE WITH STACK CHIP STRUCTURE

• US 20110291246A1
• Filed: 04/28/2011
• Published: 12/01/2011
• Est. Priority Date: 05/31/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: JO, Seung Hee, KIM, Seong Cheol
• Granted Patent: US 8,592,952 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32146 the layer connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/8113 using marks formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81132 using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/81201 Compression bonding
• CPC Class Codes: H01L 2224/81903 by means of a layer connector
• CPC Class Codes: H01L 2224/831 the layer connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material. The filling material fills a gap between the semiconductor chips.

Claims

1. A semiconductor chip comprising:

a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern including a bonding pad is formed on the first surface; and

a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material.

2. The semiconductor chip of claim 1, further comprising a second align pattern formed on the second surface of the semiconductor substrate in correspondence to the first align pattern, wherein the second align pattern is formed of a magnetic material.

3. The semiconductor chip of claim 2, wherein the first align pattern and the second align pattern have opposite polarities to each other.

4. The semiconductor chip of claim 1, further comprising:

a through-silicon via (TSV) passing through the semiconductor substrate.

5. The semiconductor chip of claim 4, wherein the first align pattern is formed in a region where the circuit pattern and the through-silicon via are not formed.

6. The semiconductor chip of claim 5, further comprising a scribe lane on at least one side of the semiconductor substrate, wherein the first align pattern is formed on the scribed lane.

7. The semiconductor chip of claim 2, wherein the first align pattern and the second align pattern are formed in plurality and arranged symmetrically to each other.

8. A semiconductor package comprising:

a plurality of stacked semiconductor chips; and

a filling material filling a gap between the semiconductor chips, wherein each of the plurality of stacked semiconductor chips comprises;

a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern including a bonding pad is formed on the first surface; and

a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material.

9. The semiconductor package of claim 8, further comprising a second align pattern formed on the second surface of each of the semiconductor chips in correspondence to the first align pattern, wherein the second align pattern is formed of a magnetic material.

10. The semiconductor package of claim 9, wherein the first align pattern and the second align pattern of each of the semiconductor chips have opposite polarities to each other.

11. The semiconductor package of claim 8, further comprising:

a through-silicon via (TSV) passing through the semiconductor substrate of each of the semiconductor chips.

12. The semiconductor package of claim 11, wherein the first align pattern of each of the semiconductor chips is formed in a region where the circuit pattern and the through-silicon via are not formed.

13. The semiconductor package of claim 12, further comprising a scribe lane on at least one side of the semiconductor substrate of each of the semiconductor chips, wherein the first align pattern is formed on the scribed lane.

14. The semiconductor package of claim 9, further comprising an interconnection formed on the lowermost semiconductor chip among the plurality of semiconductor chips and electrically connected to the plurality of semiconductor chips.

15. The semiconductor package of claim 14, further comprising a third align pattern formed on the semiconductor substrate in correspondence to the second align pattern of the lowermost semiconductor chip among the plurality of semiconductor chips.

16. The semiconductor package of claim 11, further comprising:

a redistribution film formed on the second surface of the lowermost semiconductor chip among the plurality of semiconductor chips and coupled to the TSV of the lowermost semiconductor chip; and

an insulation layer exposing a portion of the redistribution film.

17. The semiconductor package of claim 16, further comprising:

an insulation layer formed between the second surface of the lowermost semiconductor chip and the redistribution film and exposing the TSV of the lowermost semiconductor chip.

18. The semiconductor package of claim 8, further comprising a semiconductor chip formed on the uppermost semiconductor chip among the plurality of semiconductor chips, wherein the semiconductor chip comprises a fourth align pattern corresponding to the second align pattern of the uppermost semiconductor chip.

19. The semiconductor package of claim 8, wherein the filling material comprises a magnetic field shielding material.

20. A semiconductor package comprising:

a substrate comprising an interconnection;

a plurality of stacked semiconductor chips;

a filling material filling a gap between the semiconductor chips; and

a molding agent formed on the substrate to cover the plurality of semiconductor chips, wherein each of the plurality of stacked semiconductor chips comprises;

a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern including a bonding pad is formed on the first surface;

a first align pattern formed on the first surface, wherein the first align pattern is formed of a magnetic material;

a second align pattern formed on the second surface in correspondence to the first align pattern, having an opposite polarity to the first align pattern, wherein the second align pattern is formed of a magnetic material; and

a through-silicon via passing through the semiconductor substrate.