LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME

• US 20110292099A1
• Filed: 05/27/2011
• Published: 12/01/2011
• Est. Priority Date: 05/28/2010
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Moon, Myungkook, KIM, Jongwoo, Jang, Suhyuk, Nam, Hyuntaek
• Granted Patent: US 8,723,899 B2
• Time in Patent Office: Days
• US Class Current: 345/691
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2320/0204 Compensation of DC component across the pixels in flat panels
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2360/16 Calculation or use of calculated indices related to luminance levels in display data
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a liquid crystal display panel on which data lines and gate lines cross each other, a data driving circuit that converts data of an input image into positive and negative analog data voltages and outputs the data voltages to the data lines, a gate driving circuit sequentially supplying a gate pulse synchronized with the data voltages to the gate lines, and a timing controller that supplies the input image data to the data driving circuit, controls an operation timing of each of the data driving circuit and the gate driving circuit, compares the input image data with a previously stored reference data pattern, and decides whether or not the input image data is the same as the reference data pattern.

Claims

1. A liquid crystal display comprising:

a liquid crystal display panel on which data lines and gate lines cross each other;

a data driving circuit configured to convert data of an input image into positive and negative analog data voltages and output the positive and negative analog data voltages to the data lines;

a gate driving circuit configured to sequentially supply a gate pulse synchronized with the data voltages to the gate lines; and

a timing controller configured to supply the input image data to the data driving circuit, control an operation timing of each of the data driving circuit and the gate driving circuit, compare the input image data with a previously stored reference data pattern, and decide whether the input image data is the same as the reference data pattern,

wherein when the input image data is the same as the reference data pattern, the timing controller recognizes the input image data as a first problem pattern, disables an operation for counting data of a white gray level, and controls horizontal polarities of the data voltages output from the data driving circuit in a horizontal 1 dot inversion scheme,

wherein when the input image data is not the same as the reference data pattern, the timing controller recognizes the input image data as a second problem pattern, enables the operation for counting the data of the white gray level, decides a shift of a common voltage based on a count value, and controls the horizontal polarities of the data voltages output from the data driving circuit in a horizontal 2 dot inversion scheme so as to minimize the shift of the common voltage.

2. The liquid crystal display of claim 1, wherein the timing controller includes:

a first problem pattern recognition unit configured to detect the first problem pattern;

a second problem pattern recognition unit configured to detect the second problem pattern; and

a polarity control unit configured to determine a logic level of a horizontal polarity control signal based on a logic level of a first problem pattern flag received from the first problem pattern recognition unit and a logic level of a second problem pattern flag received from the second problem pattern recognition unit.

3. The liquid crystal display of claim 2, wherein the first problem pattern recognition unit extracts a sample data of a predetermined size among data of one frame of the input image, compares the extracted sample data with the reference data pattern in each subpixel, decides whether or not the sample data is the same as the reference data pattern, generates the first problem pattern flag of a high logic level when the sample data is the same as the reference data pattern, and generates the first problem pattern flag of a low logic level when the sample data is not the same as the reference data pattern.

4. The liquid crystal display of claim 2, wherein the second problem pattern recognition unit respectively maps the input image data to polarity patterns of the horizontal 1 dot inversion scheme using first and second counters enabled only when the first problem pattern flag of the low logic level is received, counts the number of data of the white gray level mapped to a positive polarity and the number of data of the white gray level mapped to a negative polarity, and obtains a first common voltage shift amount indicating a shifted amount of the common voltage when the polarities of the data voltages are inverted in the horizontal 1 dot inversion scheme,

wherein the second problem pattern recognition unit respectively maps the input image data to polarity patterns of the horizontal 2 dot inversion scheme using third and fourth counters enabled only when the first problem pattern flag of the low logic level is received, counts the number of data of the white gray level mapped to the positive polarity and the number of data of the white gray level mapped to the negative polarity, and obtains a second common voltage shift amount indicating a shifted amount of the common voltage when the polarities of the data voltages are inverted in the horizontal 2 dot inversion scheme,

wherein the second problem pattern recognition unit compares the first common voltage shift amount with the second common voltage shift amount, generates the second problem pattern flag of the high logic level when the first common voltage shift amount is greater than the second common voltage shift amount, and generates the second problem pattern flag of the low logic level when the first common voltage shift amount is less than the second common voltage shift amount.

5. The liquid crystal display of claim 2, wherein when the first problem pattern flag of the high logic level or the second problem pattern flag of the low logic level is input, the polarity control unit generates the horizontal polarity control signal of the low logic level and controls the polarities of the data voltages in the horizontal 1 dot inversion scheme specified to a default value without changing a dot inversion scheme,

wherein when the first problem pattern flag of the low logic level and the second problem pattern flag of the high logic level are input, the polarity control unit generates the horizontal polarity control signal of the high logic level and controls the polarities of the data voltages in the horizontal 2 dot inversion scheme through a change in a dot inversion scheme.

6. A method of driving a liquid crystal display including a liquid crystal display panel on which data lines and gate lines cross each other, a data driving circuit that converts digital video data into positive and negative analog data voltages and outputs the positive and negative analog data voltages to the data lines, and a gate driving circuit sequentially supplying a gate pulse synchronized with the data voltages to the gate lines, the method comprising the step of:

(A) comparing the input image data with a previously stored reference data pattern, deciding whether the input image data is the same as the reference data pattern, when the input image data is the same as the reference data pattern, recognizing the input image data as a first problem pattern, disabling an operation for counting data of a white gray level, and controlling horizontal polarities of the data voltages output from the data driving circuit in a horizontal 1 dot inversion scheme; and

(B) when the input image data is not the same as the reference data pattern, recognizing the input image data as a second problem pattern, enabling the operation for counting the data of the white gray level, deciding a shift of a common voltage based on a count value, and controlling the horizontal polarities of the data voltages output from the data driving circuit in a horizontal 2 dot inversion scheme so as to minimize the shift of the common voltage.

7. The method of claim 6, further comprising generating a horizontal polarity control signal for controlling the horizontal polarities of the data voltages output from the data driving circuit,

wherein a logic level of the horizontal polarity control signal is determined based on a logic level of a first problem pattern flag and a logic level of a second problem pattern flag.

8. The method of claim 7, wherein the step (A) includes extracting a sample data of a predetermined size among data of one frame of the input image so as to recognize the first problem pattern, comparing the extracted sample data with the reference data pattern in each subpixel, deciding whether or not the sample data is the same as the reference data pattern, generating the first problem pattern flag of a high logic level when the sample data is the same as the reference data pattern, and generating the first problem pattern flag of a low logic level when the sample data is not the same as the reference data pattern.

9. The method of claim 8, wherein the step (B) includes:

respectively mapping the input image data to polarity patterns of the horizontal 1 dot inversion scheme using first and second counters enabled only when the first problem pattern flag of the low logic level is received, counting the number of data of the white gray level mapped to a positive polarity and the number of data of the white gray level mapped to a negative polarity, and obtaining a first common voltage shift amount indicating a shifted amount of the common voltage when the polarities of the data voltages are inverted in the horizontal 1 dot inversion scheme;

respectively mapping the input image data to polarity patterns of the horizontal 2 dot inversion scheme using third and fourth counters enabled only when the first problem pattern flag of the low logic level is received, counting the number of data of the white gray level mapped to the positive polarity and the number of data of the white gray level mapped to the negative polarity, and obtaining a second common voltage shift amount indicating a shifted amount of the common voltage when the polarities of the data voltages are inverted in the horizontal 2 dot inversion scheme; and

comparing the first common voltage shift amount with the second common voltage shift amount, generating the second problem pattern flag of the high logic level when the first common voltage shift amount is greater than the second common voltage shift amount, and generating the second problem pattern flag of the low logic level when the first common voltage shift amount is less than the second common voltage shift amount.

10. The method of claim 9, wherein when the first problem pattern flag of the high logic level or the second problem pattern flag of the low logic level is input, the horizontal polarity control signal is generated at the low logic level and controls the polarities of the data voltages in the horizontal 1 dot inversion scheme specified to a default value without changing a dot inversion scheme,

wherein when the first problem pattern flag of the low logic level and the second problem pattern flag of the high logic level are input, the horizontal polarity control signal is generated at the high logic level and controls the polarities of the data voltages in the horizontal 2 dot inversion scheme through a change in a dot inversion scheme.