CMOS three-dimensional image sensor detectors having reduced inter-gate capacitance, and enhanced modulation contrast

• US 20110292380A1
• Filed: 02/16/2010
• Published: 12/01/2011
• Est. Priority Date: 02/17/2009
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Canesta Incorporated (Microsoft Corporation)
• Inventors: Bamji, Cyrus
• Granted Patent: US 8,953,149 B2
• Time in Patent Office: Days
• US Class Current: 356/141.1
• CPC Class Codes: G01J 1/42 using electric radiation detectors optical or mechanical part G01J1/04; by comparison with a reference light or electric value G01J1/10
• CPC Class Codes: G01S 17/894 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
• CPC Class Codes: G01S 7/4861 Circuits for detection, sampling, integration or read-out
• CPC Class Codes: G01S 7/4863 Detector arrays, e.g. charge-transfer gates
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14605 Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
• CPC Class Codes: H01L 27/14614 having a special gate structure
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

A CMOS detector with pairs of interdigitated elongated finger-like collection gates includes p+ implanted regions that create charge barrier regions that can intentionally be overcome. These regions steer charge to a desired collection gate pair for collection. The p+ implanted regions may be formed before and/or after formation of the collection gates. These regions form charge barrier regions when an associated collection gate is biased low. The barriers are overcome when an associated collection gate is high. These barrier regions steer substantially all charge to collection gates that are biased high, enhancing modulation contrast. Advantageously, the resultant structure has reduced power requirements in that inter-gate capacitance is reduced in that inter-gate spacing can be increased over prior art gate spacing and lower swing voltages may be used. Also higher modulation contrast is achieved in that the charge collection area of the low gate(s) is significantly reduced.

Claims

1. A CMOS-implementable sensor that generates charge responsive to detected photon energy, the sensor comprising:

a semiconductor structure;

at least one biasable gate disposed on an upper surface of said semiconductor structure;

a doping barrier region, formed in said semiconductor generally beneath a region of said gate;

wherein when a bias voltage VG is coupled to said biasable gate having bias voltage magnitude V_RELEASE<

VG<

V_COLLECT, said doping barrier region prevents said biasable gate from collecting substantially any additional charge while allowing said biasable gate to retain already collected charge; and

wherein when V_COLLECT<

VG, said magnitude VG overcomes said doping barrier region and allows collection by said detector charges collected at said biasable gate.

2. The sensor of claim 1, wherein said doping barrier is formed with p+ dopant.

3. The sensor of claim 1, wherein said doping barrier has a magnitude ranging from about 200 mV to about 300 mV.

4. The sensor of claim 1, wherein when said bias voltage VG>

1 V, said barrier region ceases to prevent said biasable gate from collecting substantially any further charge.

5. The sensor of claim 4, wherein when VG<

1 V, said biasable gate collects substantially no charge and charges generated when VG<

1 are not subsequently collected by said biasable gate due to recombination or collection elsewhere in said sensor.

6. The sensor of claim 1, wherein said doping barrier region is formed is a manner selected from (i) deposition after formation of said biasable gate, and (ii) depth of said doping barrier region is about 0.1 μ

m, (iii) width of said doping barrier region at said surface of said structure is about 0.2 μ

m, (iv) width of said doping barrier at said surface of said substrate is about three times depth of said doping barrier into said substrate, (v) width of said doping barrier at said surface of said substrate is about three times greater than width of said biasable gate, and (vi) doping concentration of said doping barrier region is about 1×

10¹⁷/cm³.

7. The sensor of claim 1, further including a second said biasable gate disposed on said surface of said substrate, said first biasable gate and said second biasable gate being finger-shaped with lengths exceeding widths, and being disposed spaced-apart and parallel to each other;

wherein said bias voltage VG coupled to said first gate is out of phase with a bias voltage coupled to said second gate;

wherein charge generated within said sensor is collected predominately at a given time by one of said first biasable gate and said second biasable gate.

8. The sensor of claim 7, wherein said sensor is in an array of like sensors, said array sensing charge in a time-of-flight system.

9. A CMOS-implementable semiconductor photodetector sensor useable in a time-of-flight (TOF) system that illuminates a target object with optical energy having a modulated periodic waveform that includes a high frequency component, the optical energy generated in response to signal provided by a TOF clock generator, the TOF system detecting with at least one said semiconductor photodetector sensor a fraction of said optical energy reflected by said target object, the semiconductor photodetector sensor comprising:

a semiconductor substrate having an optical energy sensitive region and having surface upon which reflected said optical energy can impinge onto said optical energy sensitive region;

at least one doping barrier region formed in said optical energy sensitive region of said semiconductor substrate;

a first polysilicon gate disposed on said surface of said substrate, said first polysilicon gate coupleable to a first bias clock signal synchronously generated by said TOF clock generator;

said bias clock signal having a high magnitude potential during a first bias regime during which a barrier within said doping barrier region is overcome by said high magnitude potential and at least a fraction of impinging optical energy created photocharges are collected;

said bias clock signal having a low magnitude potential during a second regime during which time a barrier within said potential barrier is insurmountable such that charges previously collected are retained by said first polysilicon gate and substantially no additional photocharges are collected by said first polysilicon gate.

10. The sensor of claim 9, wherein said doping barrier region is formed with p+ dopant.

11. The sensor of claim 9, wherein said doping barrier has a magnitude ranging from about 200 mV to about 300 mV.

12. The sensor of claim 9, wherein when said bias clock signal>

1 V, said barrier region ceases to prevent said first polysilicon gate from collecting substantially any further charge.

13. The sensor of claim 12, wherein when said bias clock signal<

1 V, said biasable gate collects substantially no charge and charges generated when VG<

1 are not subsequently collected by said biasable gate due to recombination or collection elsewhere in said sensor.

14. The sensor of claim 9, wherein said doping barrier region is formed is a manner selected from (i) deposition after formation of said first polysilicon gate, and (ii) depth of said doping barrier region is about 0.1 μ

m, (iii) width of said doping barrier region at said surface of said structure is about 0.2 μ

m, (iv) width of said doping barrier at said surface of said substrate is about three times depth of said doping barrier into said substrate, (v) width of said doping barrier at said surface of said substrate is about three times greater than width of said first polysilicon gate, and (vi) doping concentration of said doping barrier region is about 1×

10¹⁷/cm³.

15. The sensor of claim 9, further including a second said polysilicon gate gate disposed on said surface of said substrate, said first polysilicon gate and said second polysilicon gate being finger-shaped with lengths exceeding widths, and being disposed spaced-apart and parallel to each other;

wherein a second bias signal coupled to said second polysilicon gate is out of phase with said first bias voltage coupled to first polysilicon gate;

wherein charge generated within said sensor is collected predominately at a given time by one of said first polysilicon gate and said second polysilicon gate.

16. The sensor of claim 15, wherein when said first bias signal is <

1 V, said first polysilicon gate collects substantially no charge and charges generated said first bias signal is <

1 are not subsequently collected by said first polysilicon gate due to recombination or collection by said second polysilicon gate.

17. The sensor of claim 15, wherein said sensor is in an array of like sensors, said array sensing charge in a time-of-flight system.