Semiconductor Antenna Switch

• US 20110294445A1
• Filed: 05/23/2011
• Published: 12/01/2011
• Est. Priority Date: 05/25/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kondo, Masao, Goto, Satoshi
• Granted Patent: US 8,401,496 B2
• Time in Patent Office: Days
• US Class Current: 455/83
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H01P 1/213 combining or separating two or more different frequencies H01P1/215 takes precedence

Abstract

A semiconductor antenna switch has an antenna terminal, a transmission terminal and a reception terminal. The antenna switch is capable of reducing harmonic distortion even though it includes field effect transistors formed over a silicon substrate. A shunt transistor including a plurality of series-connected field effect transistors is connected between he transmission terminal and a common terminal, such as a common terminal, which may be an electrical ground. Off capacitances and/or gate widths of a plurality of the series-connected field effect transistors increase monotonically in the direction from the common terminal to the transmission terminal, or equivalently, decrease monotonically in the direction from the transmission terminal to the common terminal.

Claims

1. A semiconductor antenna switch comprising a transmission terminal, an antenna terminal, and a reception terminal, and further comprising:

(a) a plurality of first field effect transistors coupled in series between the antenna terminal and transmission terminal;

(b) a plurality of second field effect transistors coupled in series between the antenna terminal and the reception terminal, a first of the second field effect transistors being closest to the antenna terminal and a last of the second field effect transistors being closest to the reception terminal;

(c) a plurality of third field effect transistors coupled in series between the transmission terminal and a common terminal, a first of the third effect transistors being closest to the transmission terminal and a last of the third field effect transistors being closest to the common terminal; and

(d) a fourth field effect transistor coupled between the reception terminal and the common terminal, wherein;

each of the third field effect transistors has a gate electrode, a source region, a drain region, and a first off capacitance indicative of a capacitance between the source and drain regions when said each of the third field effect transistors is OFF; and

the first off capacitance of at least the first of the third field effect transistors is larger than the first off capacitance of the last of the third field effect transistors.

2. The semiconductor antenna switch according to claim 1, wherein a gate width of the first of the third field effect transistors is larger than a gate width of the last of the third field effect transistors.

3. The semiconductor antenna switch according to claim 1, wherein the first off capacitances increase monotonically from the last of the third field effect transistors to the first of the third field effect transistors.

4. The semiconductor antenna switch according to claim 3, wherein gate widths of the third field effect transistors increase monotonically from the last of the third field effect transistors to the first of the third field effect transistors.

5. The semiconductor antenna switch according to claim 4, wherein gate widths of the third field effect transistors increase on a linear function basis from the last of the third field effect transistors to the first of the third field effect transistors.

6. The semiconductor antenna switch according to claim 4, wherein gate widths of the third field effect transistors increase on a quadric function basis from the last of the third field effect transistors to the first of the third field effect transistors.

7. The semiconductor antenna switch according to claim 4, wherein:

each gate electrode of the third field effect transistors comprises a finger structure including a plurality of fingers which;

are arranged side by side, are electrically coupled to one another, and have a common finger length;

the number of fingers in the gate electrodes of the third field effect transistors increases monotonically from the last of the third field effect transistors to the first of the third field effect transistors; and

the common finger length is the same for all gate electrodes of the third field effect transistors.

8. The semiconductor antenna switch according to claim 4, wherein:

each gate electrode comprises a finger structure including a plurality of fingers which;

are arranged side by side, are electrically coupled to one another, and have a common finger length;

the number of fingers is the same for all gate electrodes of the third field effect transistors; and

the common finger length for the gate electrodes of the third field effect transistors increases monotonically from the last of the third field effect transistors to the first of the third field effect transistors.

9. The semiconductor antenna switch according to claim 1, wherein:

each of the second field effect transistors has a source region, a drain region, and a first off capacitance indicative of a capacitance between the source and drain regions when said each of the second field effect transistors is OFF; and

the first off capacitance of at least the first of the second field effect transistors is larger than the first off capacitance of the last of the second field effect transistors.

10. The semiconductor antenna switch according to claim 9, wherein a gate width of the first of the second field effect transistors is larger than a gate width of the last of the second field effect transistors.

11. The semiconductor antenna switch according to claim 9, wherein the first off capacitances increase monotonically from the last of the second field effect transistors to the first of the second field effect transistors.

12. The semiconductor antenna switch according to claim 11, wherein gate widths of the second field effect transistors increase monotonically from the last of the second field effect transistors to the first of the second field effect transistors.

13. The semiconductor antenna switch according to claim 12, wherein gate widths of the second field effect transistors increase on a linear function basis from the last of the second field effect transistors to the first of the second field effect transistors.

14. The semiconductor antenna switch according to claim 12, wherein gate widths of the second field effect transistors increase on a quadric function basis from the last of the second field effect transistors to the first of the second field effect transistors.

15. The semiconductor antenna switch according to claim 1, wherein the pluralities of the first, second, third and fourth field effect transistors are formed over a silicon oxide insulator (SOI) substrate comprised of a support substrate, an embedded insulating layer formed over the support substrate and an active layer formed over the embedded insulating layer.

24. A radio frequency (RF) communication module comprising:

a first semiconductor chip comprising a first power amplifier; and

a second semiconductor chip comprising a semiconductor antenna switch in accordance with claim 1;

wherein

an output of the first power amplifier is connected to the transmission terminal of said semiconductor antenna switch.

25. A portable phone comprising:

an antenna; and

a semiconductor antenna switch in accordance with claim 1;

wherein;

the antenna terminal of the semiconductor antenna switch is connected to the antenna.

16. A semiconductor antenna switch comprising a transmission terminal, an antenna terminal, and a reception terminal, and further comprising:

(a) a plurality of first field effect transistors coupled in series between the antenna terminal and the transmission terminal;

(b) a plurality of second field effect transistors coupled in series between the antenna terminal and the reception terminal, a first of the second field effect transistors being closest to the antenna terminal and a last of the second field effect transistors being closest to the reception terminal;

(c) a plurality of third field effect transistors coupled in series between the transmission terminal and a common terminal, a first of the third effect transistors being closest to the transmission terminal and a last of the third field effect transistors being closest to the common terminal; and

(d) a fourth field effect transistor coupled between the reception terminal and the common terminal, wherein;

each of the third field effect transistors has a gate electrode, a source region, a drain region, and a first off capacitance indicative of a capacitance between the source and drain regions when said each of the third field effect transistors is OFF;

the off capacitances are the same for all the third field effect transistors; and

a capacitive element is coupled between the source and drain regions of each of at least some of third field effect transistors, including between the source and drain regions of the first of the third field effect transistors.

17. The semiconductor antenna switch according to claim 16,

wherein a capacitive element is coupled between the source and drain regions of a next-to-last of the third field effect transistors, and

wherein the capacitance of the capacitive element coupled between the source and drain regions of the first of the third field effect transistors is larger than that of the capacitive element coupled between the source and drain regions of the next-to-last of the third field effect transistors.

18. The semiconductor antenna switch according to claim 16,

wherein a capacitive element is coupled between source and drain regions of each of the third field effect transistors other than the last of the third field effect transistors, and

wherein the capacitance increases monotonically from the capacitive element coupled between the source and drain regions of a next-to-last of the third field effect transistors to the capacitive element coupled between the source and drain regions of the first of the third field effect transistors.

19. The semiconductor antenna switch according to claim 18, wherein:

each of the third field effect transistors provided with a capacitive element has a combined capacitance comprising the off capacitance of that third field effect transistor and the capacitive element coupled between the source and drain regions of that third field effect transistor; and

the combined capacitance of the third field effect transistors increases on a linear function basis from the next-to-last of the third field effect transistors to the first of the third field effect transistors.

20. The semiconductor antenna switch according to claim 18, wherein:

each of the third field effect transistors provided with a capacitive element has a combined capacitance comprising the off capacitance of that third field effect transistor and the capacitive element coupled between the source and drain regions of that third field effect transistor; and

the combined capacitance of the third field effect transistors increases on a quadric function basis from the next-to-last of the third field effect transistors to the first of the third field effect transistors.

21. The semiconductor antenna switch according to claim 16, wherein:

each capacitive element is directly coupled between the source and drain regions.

22. The semiconductor antenna switch according to claim 16, wherein each capacitive element comprises:

a first capacitive element coupled between the source region of the third field effect transistor and the gate electrode of the third field effect transistor, and

a second capacitive element coupled between the drain region of the third field effect transistor and the gate electrode of the third field effect transistor.

23. The semiconductor antenna switch according to claim 16, wherein:

each capacitive element is directly coupled between the source and drain regions; and

the antenna switch further comprises;

a second capacitive element coupled between the source region of the third field effect transistor and the gate electrode of the third field effect transistor, and

a third capacitive element coupled between the drain region of the third field effect transistor and the gate electrode of the third field effect transistor.