AUTOMATIC ADDRESSING SCHEME FOR 2 WIRE SERIAL BUS INTERFACE

• US 20110296067A1
• Filed: 05/30/2011
• Published: 12/01/2011
• Est. Priority Date: 05/31/2010
• Status: Active Grant

• Current Assignee: Fluke Corporation (Fortive Corp.)
• Original Assignee: Fluke Corporation (Fortive Corp.)
• Inventors: Weidenkeller, Andreas
• Granted Patent: US 8,566,490 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 61/5038 for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]

Abstract

An automatic addressing bus system and method of communication comprising a main and an end device, wherein the respective bus controllers used in the main and end devices comprise multi-master capability. The main controlling device has an address known to the end device to be connected, the end device is able to actively initiate the address allocation procedure, without the need for user interaction. The method and system of the present system may be implemented using such known bus systems such as 2-wire serial buses, in particular I²C, and enables both automatic and dynamic address allocation.

Claims

1. A method for address allocation for a plurality of devices connected to a multi-master bus comprising:

by a first device, switching to master mode, requesting allocation of a second address from a controlling device in slave mode using a known first address associated with the controlling device, storing the second address and switching to slave mode.

2. The method of claim 1, further comprising:

by the controlling device, switching to master mode and communicating with the first device using the allocated second address.

3. The method of claim 1, further comprising:

connecting a second device to the bus;

by the second device, switching to master mode, requesting allocation of a third address from the controlling device in slave mode using the first address, storing the third address, and switching to slave mode.

4. The method of claim 3, further comprising:

by the controlling device, switching to master mode and communicating with the second device using the allocated third address.

5. The method of claim 1 wherein the first device is one of a plurality of devices switched to master mode, wherein the first device gains control of the bus in order to request allocation of the second address, and all other devices switch back to slave mode.

6. The method of claim 5 wherein, upon the first device having switched back to slave mode, the remaining plurality of devices switch to master mode and one of the remaining devices gains control of the bus in order to request allocation of a further address, and all other devices switch back to slave mode.

7. The method of claim 1, further comprising determining that no data traffic is on the bus before switching to master mode.

8. The method of claim 1 wherein the controlling device is preferably a communication device, which may be connected to a PC or a process master control station, and the first device is an end device such as a temperature sensor.

9. The method of claim 1 wherein all devices are initially in slave mode and the steps of switching modes and storing the addresses are carried out by means of software in the devices.

10. The method of claim 1 wherein all devices each comprise a bus controller with multi-master capability which is adapted to switch between master and slave modes.

11. The method of claim 1 wherein, in the step of requesting the known first address is a generic address, and, in response to the request, the controlling device generates a unique address associated with the requesting device from a look-up table and transmits it to the requesting device.

12. A system for address allocation for a plurality of devices connected to a multi-master bus, the system comprising:

a first device;

controlling device;

wherein the first device is adapted to;

switch to master mode and request allocation of a second address from the controlling device in slave mode using a known first address associated with the controlling device, and

store the second address and switch to slave mode.

13. The system of claim 12, wherein

the controlling device is adapted to switch to master mode and communicate with the first device using the allocated second address.

14. The system of claim 12, further comprising:

a second device connected to the bus;

wherein the second device is adapted to switch to master mode and request allocation of a third address from the controlling device in slave mode using the first address, and

store the third address, and switch to slave mode.

15. The system of claim 12 wherein the first device is one of a plurality of devices switched to master mode, wherein the first device gains control of the bus in order to request allocation of the second address, and all other devices switch back to slave mode.