FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS

• US 20110296138A1
• Filed: 05/27/2010
• Published: 12/01/2011
• Est. Priority Date: 05/27/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: VAN HANSBERGEN, ERIC, RAJAMANI, KARTHICK, GHEITH, AHMED, SPEIGHT, WILLIAM EVAN, ZHANG, LIXIN, CARTER, JOHN BRUCE, ELNOZAHY, ELMOOTAZBELLAH NABIL
• Granted Patent: US 9,934,079 B2
• Time in Patent Office: Days
• US Class Current: 712/29
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A method, system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.

Claims

1. A computer implemented method for fast remote communication and computation between processors, the computer implemented method comprising:

configuring a direct core to core communication unit (DCC) to operate with a first processor, the first processor being a remote processor;

receiving in a memory associated with the DCC a set of bytes, the set of bytes being sent from a second processor;

creating without software intervention a hardware execution context using data specified in the set of bytes at the remote processor; and

executing an operation specified in the set of bytes at the remote processor using the created context.

2. The computer implemented method of claim 1, wherein the set of bytes include information about a context available at the remote processor within which the remote processor has to execute an instruction included in the set of bytes.

3. The computer implemented method of claim 1, further comprising:

determining whether the set of bytes form a complete instruction, wherein the executing is responsive to the determining being positive.

4. The computer implemented method of claim 1, wherein executing the set of bytes comprises:

loading the bytes using a load instruction that loads the set of bytes at the remote processor for computation without requiring a first thread for reading the contents of the set of bytes and a second thread for executing the contents of the set of bytes.

5. The computer implemented method of claim 1, wherein executing the set of bytes further comprises:

loading the bytes using an instruction that loads the set of bytes at the remote processor for computation without requiring sending an interrupt to the remote processor.

6. The computer implemented method of claim 1, further comprising:

assessing whether the set of bytes is the first in a FIFO queue in the memory, wherein the executing is responsive to the assessing being affirmative.

7. The computer implemented method of claim 1, further comprising:

assessing whether the set of bytes is blocked from execution, wherein the executing is responsive to the assessing being negative.

8. The computer implemented method of claim 1, wherein the set of bytes are sent by a thread executing on the second processor.

9. The computer implemented method of claim 8, further comprising:

composing, using the thread, the set of bytes; and

writing the set of bytes directly to the memory of the DCC of the remote processor.

10. The computer implemented method of claim 1, wherein the set of bytes are sent using a store instruction that permits the second processor to write directly to the memory of the DCC of the remote processor.

11. The computer implemented method of claim 1, wherein the memory is a static random access memory (SRAM).

12. The computer implemented method of claim 1, wherein the memory is configured to store a plurality of sets of bytes in a first-in first-out (FIFO) queue.

13. The computer implemented method of claim 1, further comprising:

enabling the second processor to write to the memory of the DCC of the remote processor; and

configuring the remote processor to allow the second processor to write to the memory of the DCC of the remote processor.

14. The computer implemented method of claim 1, wherein arrival of the set of bytes in the memory triggers the executing without an interrupt being sent to the remote processor.

15. An apparatus for fast remote communication and computation between processors, comprising:

a first processor, the first processor being a remote processor;

a direct core to core communication unit (DCC) configured to operate with the first processor; and

a memory associated with the DCC, the memory receiving a set of bytes, the set of bytes being sent from a second processor, wherein the remote processor executes an operation specified in the set of bytes using a hardware execution context that is created without software intervention by using data specified in the set of bytes.

16. The apparatus of claim 15, wherein the set of bytes include information about a context available at the remote processor within which the remote processor has to execute an instruction included in the set of bytes.

17. The apparatus of claim 15, wherein the executing is responsive to the set of bytes forming a complete instruction.

18. The apparatus of claim 15, wherein the remote processor executes the set of bytes responsive to loading the bytes using a load instruction that loads the set of bytes at the remote processor for computation without requiring a first thread for reading the contents of the set of bytes and a second thread for executing the contents of the set of bytes.

19. The apparatus of claim 15, wherein the remote processor executes the set of bytes responsive to loading the bytes using an instruction that loads the set of bytes at the remote processor for computation without requiring sending an interrupt to the remote processor.

20. The apparatus of claim 15, wherein the remote processor executes the set of bytes responsive to the set of bytes occupying first logical position in a FIFO queue in the memory.

21. The apparatus of claim 15, wherein the remote processor executes the set of bytes responsive to the set of bytes not being blocked from execution.

22. The apparatus of claim 15, wherein the set of bytes are sent by a thread executing on the second processor.

23. The apparatus of claim 15, wherein the memory is a static random access memory (SRAM).

24. The apparatus of claim 15, wherein the memory is configured to store a plurality of sets of bytes in a first-in first-out (FIFO) queue.

25. The apparatus of claim 15, further comprising:

a first configuration enabling the second processor to write to the memory of the DCC of the remote processor; and

a second configuration configuring the remote processor to allow the second processor to write to the memory of the DCC of the remote processor.

26. The apparatus of claim 15, wherein arrival of the set of bytes in the memory triggers the executing without an interrupt being sent to the remote processor.

27. A data processing system for fast remote communication and computation between processors, the data processing system comprising:

a storage device including a storage medium, wherein the storage device stores computer usable program code; and

a processor, wherein the processor executes the computer usable program code, and wherein the computer usable program code comprises;

computer usable code for configuring a direct core to core communication unit (DCC) to operate with the processor, the processor being a remote processor;

computer usable code for receiving in a memory associated with the DCC a set of bytes, the set of bytes being sent from a second processor;

computer usable code for creating without software intervention a hardware execution context using data specified in the set of bytes at the remote processor; and

computer usable code for executing an operation specified in the set of bytes at the remote processor using the created context.

28. The data processing system of claim 27, wherein the set of bytes include information about a context available at the remote processor within which the remote processor has to execute an instruction included in the set of bytes.

29. The data processing system of claim 27, further comprising:

computer usable code for determining whether the set of bytes form a complete instruction, wherein the executing is responsive to the determining begin positive.

30. The data processing system of claim 27, wherein executing the set of bytes comprises:

computer usable code for loading the bytes using a load instruction that loads the set of bytes at the remote processor for computation without requiring a first thread for reading the contents of the set of bytes and a second thread for executing the contents of the set of bytes.

31. The data processing system of claim 27, wherein executing the set of bytes further comprises:

computer usable code for loading the bytes using an instruction that loads the set of bytes at the remote processor for computation without requiring sending an interrupt to the remote processor.

32. The data processing system of claim 27, further comprising:

computer usable code for assessing whether the set of bytes is the first in a FIFO queue in the memory, wherein the executing is responsive to the assessing being affirmative.

33. The data processing system of claim 27, further comprising:

computer usable code for assessing whether the set of bytes is blocked from execution, wherein the executing is responsive to the assessing being negative.

34. The data processing system of claim 27, wherein the set of bytes are sent by a thread executing on the second processor.

35. The data processing system of claim 34, further comprising:

computer usable code for composing, using the thread, the set of bytes; and

computer usable code for writing the set of bytes directly to the memory of the DCC of the remote processor.