DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK AND POWER GATING

• US 20110296222A1
• Filed: 12/24/2010
• Published: 12/01/2011
• Est. Priority Date: 06/01/2010
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: Intel Corporation
• Inventors: Looi, Lily Pao, Jourdan, Stephan J., Tan, Sin S., Srinivasan, Srikanth T., Radhakrishnan, Sivakumar
• Granted Patent: US 8,782,456 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.

Claims

1. A integrated circuit device comprising:

a processor; and

an Integrated Input/Output (IIO) logic coupled to the processor,

wherein at least a portion of the IIO logic is to enter a lower power consumption state based on a power reduction sequence.

2. The device of claim 1, further comprising a power management unit, coupled to the IIO logic to cause the portion of the IIO logic to enter lower power consumption state.

3. The device of claim 1, wherein the power reduction sequence is based on coarse clock gating and a plurality of power sequence gating modes.

4. The device of claim 3, wherein the plurality of power sequence gating modes are to comprise:

static clock gating, dynamic clock gating, full clock gating, pre-sleep, light sleep, or deep sleep modes.

5. The device of claim 4, wherein the static clock gating mode is to comprise clock gating one or more inactive blocks of the IIO logic based on:

one or more features being disabled during operation or one or more interfaces not being supported.

6. The device of claim 4, wherein the dynamic clock gating mode is to comprise clock gating one or more inactive blocks of the IIO logic when the one or more blocks become inactive during runtime.

7. The device of claim 4, wherein the full clock gating mode is to comprise full coarse clock gating one or more blocks of the IIO logic.

8. The device of claim 4, wherein the pre-sleep mode is to comprise preparing a phase locked loop of the IIO logic for shut down.

9. The device of claim 4, wherein the light sleep mode is to comprise shutting down an phase locked loop of the IIO logic.

10. The device of claim 4, wherein the deep sleep mode is to comprise power gating one or more blocks of the IIO logic.

11. The device of claim 3, wherein the coarse clock gating corresponds to gating off an entire cluster or block of IIO hardware when idle or not in use.

12. The device of claim 1, wherein one or more inactive blocks of the IIO are to be coarse clock gated.

13. The device of claim 12, wherein the one or more inactive blocks are to be determined based on:

one or more features being disabled during operation, one or more interfaces not being supported, or one or more blocks are idle as no traffic or transaction is occurring during runtime.

14. The device of claim 1, wherein the processor is to comprise one or more processor cores.

15. A method comprising:

generating a signal from a power management unit of an IIO logic to cause at least a portion of an IIO logic to enter a lower power consumption state based on a power reduction sequence,

wherein the power reduction sequence is based on coarse clock gating and a plurality of power sequence gating modes.

16. The method of claim 15, wherein the plurality of power sequence gating modes are to comprise:

static clock gating, dynamic clock gating, full clock gating, pre-sleep, light sleep, or deep sleep modes.

17. The method of claim 15, further comprising clock gating one or more inactive blocks of the IIO logic based on:

one or more features being disabled during operation or one or more interfaces not being supported.

18. The method of claim 15, further comprising clock gating one or more inactive blocks of the IIO logic when the one or more blocks become inactive during runtime.

19. The method of claim 15, further comprising full coarse clock gating one or more blocks of the IIO logic.

20. The method of claim 15, further comprising preparing an phase locked loop of the IIO logic for shut down.

21. The method of claim 15, further comprising shutting down a phase locked loop of the IIO logic.

22. The method of claim 15, further comprising power gating one or more blocks of the IIO logic.

23. The method of claim 15, wherein the coarse clock gating corresponds to gating off an entire cluster or block of IIO hardware when idle or not in use.

24. The method of claim 15, further comprising communicating data between a system memory and one or more I/O devices via the IIO logic.

25. A system comprising:

a system memory to store data;

a processor to access the stored data; and

an Integrated Input/Output (IIO) logic coupled to the processor,

wherein at least a portion of the IIO logic is to enter a lower power consumption state based on a power reduction sequence.

26. The system of claim 25, further comprising a power management unit, coupled to the IIO logic to cause the portion of the IIO logic to enter lower power consumption state.

27. The system of claim 25, wherein the power reduction sequence is based on coarse clock gating and a plurality of power sequence gating modes.

28. The system of claim 27, wherein the plurality of power sequence gating modes are to comprise:

static clock gating, dynamic clock gating, full clock gating, pre-sleep, light sleep, or deep sleep modes.

29. The system of claim 28, wherein the static clock gating mode is to comprise clock gating one or more inactive blocks of the IIO logic based on:

one or more features being disabled during operation or one or more interfaces not being supported.

30. The system of claim 28, wherein the light sleep mode is to comprise shutting down an phase locked loop of the IIO logic