DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK AND POWER GATING
First Claim
Patent Images
1. A integrated circuit device comprising:
- a processor; and
an Integrated Input/Output (IIO) logic coupled to the processor,wherein at least a portion of the IIO logic is to enter a lower power consumption state based on a power reduction sequence.
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Abstract
Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
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Citations
30 Claims
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1. A integrated circuit device comprising:
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a processor; and an Integrated Input/Output (IIO) logic coupled to the processor, wherein at least a portion of the IIO logic is to enter a lower power consumption state based on a power reduction sequence. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method comprising:
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generating a signal from a power management unit of an IIO logic to cause at least a portion of an IIO logic to enter a lower power consumption state based on a power reduction sequence, wherein the power reduction sequence is based on coarse clock gating and a plurality of power sequence gating modes. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A system comprising:
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a system memory to store data; a processor to access the stored data; and an Integrated Input/Output (IIO) logic coupled to the processor, wherein at least a portion of the IIO logic is to enter a lower power consumption state based on a power reduction sequence. - View Dependent Claims (26, 27, 28, 29, 30)
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Specification