OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES

• US 20110296272A1
• Filed: 05/28/2010
• Published: 12/01/2011
• Est. Priority Date: 05/28/2010
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Rub, Bernardo, Sridharan, Arvind, Buch, Bruce D., Patapoutian, Ara
• Granted Patent: US 8,572,457 B2
• Time in Patent Office: Days
• US Class Current: 714/755
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence

Abstract

Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.

Claims

1. A solid state memory device, comprising:

multiple data blocks, each block comprising an array of memory cells arranged in a plurality of pages;

encoder circuitry configured to encode data into inner code words and symbol-based outer code words; and

modulator circuitry configured to store the inner code words and the symbol-based outer code words in the memory cells of the multiple blocks, the modulator circuitry configured to store one or more inner code words in each page of each block and to store one or more symbols of each outer code word in at least one page of each block.

2. The device of claim 1, further comprising multiple die, each of the multiple blocks is arranged respectively on one of the multiple die.

3. The device of claim 1, wherein the modulator circuitry is configured to store only one outer code word symbol in one page of each of the multiple blocks.

4. The device of claim 1, wherein the modulator circuitry is configured to store a plurality of outer code word symbols in one page of each of the multiple blocks.

5. The device of claim 1, wherein:

the pages of each block are arranged in multiple planes; and

at least one symbol of each outer codeword is stored in each page of the multiple planes.

6. The device of claim 1, wherein:

the pages of each block are arranged in an even plane and an odd plane; and

the modulator circuitry is configured to store at least one symbol of each outer codeword in an even plane page of each block and at least one symbol of each outer codeword in an odd plane page of the block.

7. The device of claim 1, wherein the encoder circuitry is configured to encode the data into the outer code words using a Reed-Solomon code having dmin greater than or equal to 2.

8. The device of claim 1, wherein the memory cells comprise multiple level memory cells capable of storing x bits, where x>

1.

9. The device of claim 8, wherein the pages of the memory cell array are physical pages and each of the physical pages comprises a logical page for each of the x bits.

10. The device of claim 1, further comprising:

demodulator circuitry configured to read the memory cells of the memory device; and

decoder circuitry configured to decode the inner code words and the outer code words and to correct errors in the inner code words and the outer code words.

11. The device of claim 10, wherein the decoder circuitry is configured to iterate between correcting the outer code words and correcting the inner code words.

12. A method of operating a solid state memory device including multiple blocks, each block comprising an array of memory cells arranged in a plurality of pages, the method comprising:

encoding data into inner code words and outer code words, the inner code words comprising data and parity information, each page of each block storing at least one inner code word, the outer code words comprising data symbols and parity symbols, one or more pages of each block storing one or more symbols of each outer code word;

reading the inner code words and the outer code words from the memory device;

correcting errors in the data using the inner code words and the outer code words; and

providing an error corrected output from the corrected data.

13. The method of claim 12, wherein the memory device includes multiple memory chips and each of the multiple blocks is arranged respectively on one of the multiple chips.

14. The method of claim 12, wherein storing the inner code words and the outer code words in the memory device comprises storing a plurality of outer code word symbols in one page of each of the multiple blocks.

15. The method of claim 12, wherein the pages of each block are arranged in multiple planes, and storing the inner code words and the outer code words in the memory device comprises storing at least one symbol of each outer codeword in each page of the multiple planes.

16. The method of claim 12, wherein the outer code words comprise a Reed-Solomon code having dmin greater than or equal to 2.

17. The method of claim 12, storing the inner code words and the outer code words in the memory device comprises storing only one outer code word symbol in one page of each of the multiple blocks.

18. The method of claim 12, wherein the memory cells comprise multiple level memory cells capable of storing x bits, where x>

1.

19. The method of claim 12, wherein symbols of the outer code words are interleaved in each page.

20. The method of claim 12, wherein correcting errors in the data using the inner code words and the outer code words comprises iterating between correcting the outer code words and correcting the inner code words.