SEMICONDUCTOR DEFECT INTEGRATED PROJECTION METHOD AND DEFECT INSPECTION SUPPORT APPARATUS EQUIPPED WITH SEMICONDUCTOR DEFECT INTEGRATED PROJECTION FUNCTION
First Claim
1. A semiconductor defect inspection support apparatus, comprising:
- a design layout data read part that acquires design layout data including location information of design circuit patterns to be used in semiconductor fabrication steps;
a wafer-chip information read part that acquires, from among data concerning a wafer on which a plurality of the design circuit patterns are formed per chip, wafer-chip information including at least design cell location information;
a defect data read part that acquires defect data including location information of defects that occurred in the steps;
a design layout data tracing processing part that creates a design layout data defect integrated projection display view by performing, based on the design layout data and the wafer-chip information, an integrated projection process on, among the design layout data, design layout data for a step in which a defect occurred and the defect data; and
a defect integrated projection display apparatus that displays the design layout data defect integrated projection display view.
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Accused Products
Abstract
The present invention comprises: a design layout data read part that acquires design layout data including location information of design circuit patterns used in steps of semiconductor fabrication; a wafer-chip information read part that acquires, from among data concerning a wafer on which a plurality of the design circuit patterns are formed per chip, wafer-chip information including at least design cell location information; a defect data read part that acquires defect data including location information of defects that occurred in the steps; a design layout data tracing processing part that creates a design layout data defect integrated projection display view by performing, based on the design layout data and the wafer-chip information, an integrated projection process on, among the design layout data, design layout data for a step in which a defect occurred and the defect data; and a defect integrated projection display apparatus that displays the design layout data defect integrated projection display view.
33 Citations
9 Claims
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1. A semiconductor defect inspection support apparatus, comprising:
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a design layout data read part that acquires design layout data including location information of design circuit patterns to be used in semiconductor fabrication steps; a wafer-chip information read part that acquires, from among data concerning a wafer on which a plurality of the design circuit patterns are formed per chip, wafer-chip information including at least design cell location information; a defect data read part that acquires defect data including location information of defects that occurred in the steps; a design layout data tracing processing part that creates a design layout data defect integrated projection display view by performing, based on the design layout data and the wafer-chip information, an integrated projection process on, among the design layout data, design layout data for a step in which a defect occurred and the defect data; and a defect integrated projection display apparatus that displays the design layout data defect integrated projection display view.
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2. A defect inspection support apparatus that is used by being connected to a plurality of information storage apparatuses in each of which are stored inspection results of defect locations with respect to circuit patterns of a plurality of layers forming a semiconductor device and design layout information with respect to the circuit patterns of the plurality of layers, and that executes a supporting operation for the defect inspection by displaying on a screen the inspection results and design layout information, the defect inspection support apparatus comprising:
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means that, using coordinate information of a predetermined reference location, executes first origin alignment that aligns a coordinate origin of a coordinate system through which the defect locations are described and a coordinate origin of a coordinate system that it has itself, and second origin alignment that aligns a coordinate origin of a coordinate system through which the design layout information is described and the coordinate origin of the coordinate system that it has itself; means that generates a defect integrated projection image by synthesizing a circuit pattern obtained from the design layout information with the defects; and screen display means that displays the defect integrated projection image. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9)
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Specification