THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD OF THE SAME

• US 20110297930A1
• Filed: 06/01/2011
• Published: 12/08/2011
• Est. Priority Date: 06/04/2010
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: CHOI, Seung-Ha, Chung, Kyoung-Jae, Lee, Woo-Geun
• Granted Patent: US 9,184,090 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A TFT display panel having a high charge mobility and making it possible to obtain uniform electric characteristics with respect to a large-area display is provided as well as a manufacturing method thereof. A TFT display panel includes a gate electrode formed on an insulation substrate, a first gate insulting layer formed of SiNx on the gate electrode, a second gate insulting layer formed of SiOx on the first gate insulting layer, an oxide semiconductor layer formed to overlap the gate electrode and having a channel part, and a passivation layer formed of SiOx on the oxide semiconductor layer and the gate electrode, and the passivation layer includes a contact hole exposing the drain electrode. The contact hole has a shape in which the passivation layer of a portion directly exposed together with a metal occupies an area smaller than the upper passivation layer.

Claims

1. A TFT display panel comprising:

a gate electrode formed on an insulation substrate;

a first gate insulting layer formed on the gate electrode;

a second gate insulting layer formed of at least one of silicon oxide (SiOx), aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, and tungsten oxide on the first gate insulting layer;

an oxide semiconductor layer overlapping the gate electrode and having a channel part;

a source electrode and a drain electrode formed on the oxide semiconductor layer to be separated from each other; and

a passivation layer formed on the source electrode and the drain electrode and having a first contact hole exposing the drain electrode,

wherein the first contact hole has a shape in which the cross-sectional area increases from the bottom surface at the drain electrode upward.

2. The TFT display panel of claim 1, wherein:

the oxide semiconductor layer comprises an oxide of a material selected from among Zn, In, Ga, Sn Cd, Ge, Pb, Sr, Ca, Ni, Cu, Sb, Ba, Sc, Y, Nb, Ta, Hf, Nd, metal elements of groups 12, 13, and 14 of the periodic table, and combinations thereof.

3. The TFT display panel of claim 2, wherein:

the passivation layer includes a first passivation layer formed of at least one of silicon oxide (SiOx), aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, and tungsten oxide on the oxide semiconductor layer, and a second passivation layer formed of one of SiON, SiNx, and combinations of SiON and SiNx on the first passivation layer.

4. The TFT display panel of claim 3, wherein:

a sidewall of the first contact hole has a structure in which a gradient at the first passivation layer is smaller than a gradient at the second passivation layer.

5. The TFT display panel of claim 2, wherein:

the first gate insulating layer has a thickness of about 250 nm to about 500 nm, and the second gate insulating layer has a thickness of about 30 nm to about 100 nm.

6. The TFT display panel of claim 1, wherein:

the passivation layer includes a first passivation layer formed of at least one of silicon oxide (SiOx), aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, and tungsten oxide on the oxide semiconductor layer, and a second passivation layer formed of one of SiON, SiNx, and combinations of SiON and SiNx on the first passivation layer.

7. The TFT display panel of claim 6, wherein:

the first gate insulating has a thickness of about 250 nm to about 500 nm, and the second gate insulating layer has a thickness of about 30 nm to about 100 nm.

8. The TFT display panel of claim 1, wherein:

the first gate insulating layer has a thickness of about 250 nm to about 500 nm, and the second gate insulating layer has a thickness of about 30 nm to about 100 nm.

9. The TFT display panel of claim 1, further comprising:

a gate line connected to the gate electrode and having a gate pad part,

wherein the passivation layer, the second gate insulating layer, and the first gate insulating layer has a second contact hole exposing the gate pad part, and

the second contact hole has a shape in which the cross-sectional area increases from the bottom surface at the gate pad part upward.

10. The TFT display panel of claim 9, wherein:

the passivation layer includes a first passivation layer formed of SiOx on the oxide semiconductor layer, and a second passivation layer formed of one SiON, SiNx, and combinations of SiON and SiNx on the first passivation layer, and

a sidewall of the second contact hole has a first slope, a second slope less steep than the first slope, and a third slope steeper than the second slope from the bottom surface upward.

11. The TFT display panel of claim 10, wherein:

the first gate insulating layer has a thickness of about 250 nm to about 500 nm, and the second gate insulating layer has a thickness of about 30 nm to about 100 nm.

12. The TFT display panel of claim 9, wherein:

the first gate insulating layer has a thickness of about 250 nm to about 500 nm, and the second gate insulating layer may be formed to have a thickness of about 30 nm to about 100 nm.

13. A method of manufacturing a TFT display panel comprising:

forming a gate electrode on an insulation substrate;

forming a first gate insulting layer on the gate electrode;

forming a second gate insulting layer of at least one of silicon oxide (SiOx), aluminum oxide, titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, and tungsten oxide on the first gate insulting layer;

forming an oxide semiconductor layer on the second gate insulting layer;

forming a source electrode and a drain electrode on the oxide semiconductor layer to be separated from each other; and

forming a passivation layer, which has a first contact hole and contains an oxide, on the source electrode and the drain electrode,

wherein the first contact hole has a shape in which the cross-sectional area increases from the bottom surface upward.

14. The method of claim 13, wherein:

forming the first contact hole includes performing a dry etch using an etch gas comprising SF₆ and O₂, and performing a dry etch using an etch gas comprising a carbon-fluoride gas and a SF₆ and O₂.

15. The method of claim 14, wherein:

The carbon-fluoride gas comprises at least one of C₄F₈, C₂F₆, CF₄, and CHF₃.

16. The method of claim 15, wherein:

the passivation layer includes a first passivation layer formed of SiOx on the oxide semiconductor layer, and a second passivation layer formed of one SiON, SiNx, and combinations of SiON and SiNx on the first passivation layer.

17. The method of claim 16, wherein:

the first gate insulating layer has a thickness of about 250 nm to about 500 nm, and the second gate insulating layer has a thickness of about 30 nm to about 100 nm.

18. The method of claim 13, further comprising:

forming a gate line and a gate pad part both connected to the gate electrode, and

forming a second contact hole passing through the passivation layer, the second gate insulating layer, and the first gate insulating layer to expose the gate pad part, wherein the second contact hole has a shape in which the cross-sectional area increases from the bottom surface at the gate pad part upward.

19. The method of claim 18, wherein:

forming the first contact hole includes performing a dry etch using an etch gas comprising a SF₆ and O₂, and performing a dry etch using an etch gas comprising a carbon-fluoride gas and a SF₆ and O₂.

20. The method of claim 19, wherein:

The carbon-fluoride gas comprises at least one of C₄F₈, C₂F₆, CF₄, and CHF₃.

21. The method of claim 20, wherein:

the first gate insulating layer has a thickness of about 250 nm to about 500 nm, and the second gate insulating layer may has a thickness of about 30 nm to about 100 nm.

22. The method of claim 18, wherein:

the passivation layer includes a first passivation layer formed of SiOx on the oxide semiconductor layer, and a second passivation layer formed of one SiON, SiNx, and combinations of SiON and SiNx on the first passivation layer, and

a sidewall of the second contact hole has a first slope, a second slope less steep than the first slope, and a third slope steeper than the second slope from the bottom surface upward.