Vertical Structure Semiconductor Memory Devices And Methods Of Manufacturing The Same

• US 20110298013A1
• Filed: 04/07/2011
• Published: 12/08/2011
• Est. Priority Date: 06/07/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Han-soo, Shim, Sun-il, Hwang, Sung-Min
• Granted Patent: US 8,492,797 B2
• Time in Patent Office: Days
• US Class Current: 257/208
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

Claims

1. A semiconductor memory device comprising:

a semiconductor region extending vertically from a first region of a substrate;

a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, the plurality of gate electrodes being separated from one another and being disposed along a sidewall of the semiconductor region;

a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes;

a substrate contact electrode extending vertically from an impurity-doped second region of the substrate; and

an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

2. The semiconductor memory device of claim 1, wherein the semiconductor region, the plurality of gate electrodes, and the gate dielectric layer form a memory cell string including selection transistors and memory cell transistors disposed between the selection transistors.

3. The semiconductor memory device of claim 2, wherein the substrate has a same conductivity type as impurities of the impurity-doped second region, and data stored in the memory cell transistors is erasable by applying an erasing voltage to the substrate via the substrate contact electrode.

4. The semiconductor memory device of claim 1, wherein the substrate has a conductivity type opposite to impurities of the impurity-doped second region, and the second region corresponds to a source region of a transistor including a lowermost gate electrode from among the plurality of gate electrodes.

5. The semiconductor memory device of claim 1, further comprising:

a spacer between the substrate contact electrode and at least one of the plurality of gate electrodes.

6. The semiconductor memory device of claim 5, wherein the at least one of the plurality of gate electrodes is a gate electrode of a ground selection transistor of a memory cell string.

7. The semiconductor memory device of claim 5, wherein the gate dielectric layer comprises:

a tunnel insulating layer, a charge storage layer and a barrier insulating layer that are sequentially stacked on the semiconductor region;

wherein

the spacer is formed of a material having an etch selectivity with respect to the barrier insulating layer.

8. The semiconductor memory device of claim 1, wherein the insulating region insulates sidewalls of the substrate contact electrode from the plurality of gate electrodes.

9-16. -16. (canceled)

17. A semiconductor memory device comprising:

a substrate extending in a first direction and a second direction substantially perpendicular to the first direction;

pillar-shaped semiconductor regions extending from the substrate in a third direction, the third direction being substantially perpendicular to the first direction and the second direction, and the pillar-shaped semiconductor regions being separated from each other in the first direction and the second direction;

a plurality of memory cell strings extending in the third direction along sidewalls of the pillar-shaped semiconductor regions;

at least one impurity region defined in the substrate between the plurality of memory cell strings and extending in the second direction;

at least one substrate contact electrode coupled to the at least one impurity region in the substrate; and

a plurality of insulating regions formed as air gaps between the at least one substrate contact electrode and the plurality of memory cell strings.

18. The semiconductor memory device of claim 17, wherein the at least one substrate contact electrode extends in a line pattern in the second direction along the at least one impurity region.

19. The semiconductor memory device of claim 17, wherein the at least one substrate contact electrode is disposed on the at least one impurity region, separated from one another other in the second direction, and have a pillar-shape extending in the third direction.

20. (canceled)

21. A semiconductor memory device having a three-dimensional structure, the semiconductor memory device comprising:

at least one memory cell string disposed on a first region of a surface of a substrate and extending in a first direction, the first direction being substantially perpendicular to the surface of the substrate; and

at least one substrate contact electrode disposed on a second region of the substrate and extending in the first direction;

wherein

the substrate contact electrode is insulated from the at least one memory cell string by an air gap.

22. The semiconductor memory device of claim 21, wherein the at least one memory cell string comprises:

at least one string selection transistor, a plurality of memory cell transistors and at least one ground selection transistor connected serially between a bit line and a common source line;

wherein

a gate electrode of at least one of the at least one string selection transistor, the plurality of memory cell transistors and the at least one ground selection transistor are insulated from the substrate contact electrode by the air gap.

23. The semiconductor memory device of claim 22, wherein gate electrodes of each of the at least one string selection transistor, the plurality of memory cell transistors and the at least one ground selection transistor are insulated from the substrate contact electrode by the air gap.

24. The semiconductor memory device of claim 22, further comprising:

a spacer formed between the substrate contact electrode and a gate electrode of at least one other of the at least one string selection transistor, the plurality of memory cell transistors and the at least one ground selection transistor.

25. The semiconductor memory device of claim 22, wherein gate electrodes of the at least one string selection transistor, the plurality of memory cell transistors and the at least one ground selection transistor are insulated from one another by air gaps.

26. The semiconductor memory device of claim 21, wherein the at least one substrate contact electrode includes a plurality of substrate contact electrodes, the plurality of substrate contact electrodes being insulated from the at least one memory cell string and from one another by air gaps.

27. The semiconductor memory device of claim 21, wherein a height of the at least one substrate contact electrode is less than a height of the at least one memory cell string.

28. The semiconductor memory device of claim 27, wherein the at least one memory cell string is insulated from an other memory cell string by an air gap.

29-31. -31. (canceled)