Semiconductor Device and Method of Forming EMI Shielding Layer with Conductive Material Around Semiconductor Die

• US 20110298101A1
• Filed: 06/02/2010
• Published: 12/08/2011
• Est. Priority Date: 06/02/2010
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Pagaila, Reza A., Carson, Flynn, Yoon, Seung Uk
• Granted Patent: US 9,484,279 B2
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0217 Alignment aids
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11 : Manufacturing methods
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13027 : the bump connector being offset with respect to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/215 : Material
• CPC Class Codes: H01L 2224/221 : Disposition
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/95001 : involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06537 : Electromagnetic shielding
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/06 : characterised by the material of the container or its electrical properties
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/115 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.

Claims

1. A method of making a semiconductor device, comprising:

providing a temporary carrier covered by an interface layer;

mounting a plurality of first semiconductor die over the interface layer;

depositing an encapsulant over the first semiconductor die and temporary carrier;

forming a flat shielding layer over the encapsulant;

forming a channel through the flat shielding layer and encapsulant down to the interface layer;

depositing conductive material in the channel electrically connected to the flat shielding layer;

removing the interface layer and temporary carrier;

forming an interconnect structure over conductive material, encapsulant, and first semiconductor die, the conductive material being electrically connected to the interconnect structure; and

singulating the conductive material to separate the first semiconductor die.

2. The method of claim 1, wherein the conductive material extends into the interconnect structure.

3. The method of claim 1, wherein the conductive material terminates at a boundary between the encapsulant and interconnect structure.

4. The method of claim 1, further including electrically connecting the conductive material through the interconnect structure to a ground point.

5. The method of claim 1, further including providing side-by-side first semiconductor die each covered by the flat shielding layer and surrounded by the conductive material.

6. The method of claim 1, further including mounting a second semiconductor die over the first semiconductor die, wherein the shielding layer covers the second semiconductor die and the conductive material surrounds the first and second semiconductor die.

7. The method of claim 1, further including mounting a second semiconductor die over the first semiconductor die, wherein the shielding layer covers the second semiconductor die and the conductive material surrounds only the second semiconductor die.

8. A method of making a semiconductor device, comprising:

providing a carrier;

mounting a first semiconductor die over the carrier;

depositing a first encapsulant over the first semiconductor die and carrier;

forming a shielding layer over the first encapsulant;

forming a channel through the shielding layer and first encapsulant down to the carrier;

depositing conductive material in the channel electrically connected to the shielding layer;

removing the carrier; and

forming a first interconnect structure over conductive material, first encapsulant, and first semiconductor die, the conductive material being electrically connected to the first interconnect structure.

9. The method of claim 8, wherein the conductive material extends into the first interconnect structure.

10. The method of claim 8, wherein the conductive material terminates at a boundary between the first encapsulant and first interconnect structure.

11. The method of claim 8, further including electrically connecting the conductive material through the first interconnect structure to a ground point.

12. The method of claim 8, further including:

forming a plurality of conductive vias through the first encapsulant;

forming a second interconnect structure over the first encapsulant;

mounting a second semiconductor die over the second interconnect structure;

depositing a second encapsulant over the second semiconductor die; and

forming the shielding layer over the second encapsulant, wherein the conductive material surrounds the first and second semiconductor die.

13. The method of claim 8, further including

forming a plurality of conductive vias through the first encapsulant;

forming a second interconnect structure over the first encapsulant;

mounting a second semiconductor die over the first semiconductor die;

depositing a second encapsulant over the second semiconductor die; and

forming the shielding layer over the second encapsulant, wherein the conductive material surrounds only the second semiconductor die.

14. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

depositing a first encapsulant over the first semiconductor die;

forming a shielding layer over the first encapsulant;

forming a channel through the shielding layer and first encapsulant;

depositing conductive material in the channel electrically connected to the shielding layer; and

forming a first interconnect structure over conductive material, first encapsulant, and first semiconductor die.

15. The method of claim 14, wherein the conductive material is electrically connected to the first interconnect structure.

16. The method of claim 14, wherein the conductive material extends into the first interconnect structure.

17. The method of claim 14, wherein the conductive material terminates at a boundary between the first encapsulant and first interconnect structure.

18. The method of claim 14, further including electrically connecting the conductive material through the first interconnect structure to a ground point.

19. The method of claim 14, further including:

forming a plurality of conductive vias through the first encapsulant;

forming a second interconnect structure over the first encapsulant;

mounting a second semiconductor die over the second interconnect structure;

depositing a second encapsulant over the second semiconductor die; and

forming the shielding layer over the second encapsulant, wherein the conductive material surrounds the first and second semiconductor die.

20. The method of claim 14, further including

forming a plurality of conductive vias through the first encapsulant;

forming a second interconnect structure over the first encapsulant;

mounting a second semiconductor die over the first semiconductor die;

depositing a second encapsulant over the second semiconductor die; and

forming the shielding layer over the second encapsulant, wherein the conductive material surrounds only the second semiconductor die.

21. A semiconductor device, comprising:

a first semiconductor die;

a first encapsulant deposited over the first semiconductor die;

a shielding layer formed over the first encapsulant;

a channel formed through the shielding layer and first encapsulant;

a conductive material deposited in the channel electrically connected to the shielding layer; and

a first interconnect structure formed over conductive material, first encapsulant, and first semiconductor die.

22. The semiconductor device of claim 21, wherein the conductive material is electrically connected to the first interconnect structure.

23. The semiconductor device of claim 21, wherein the conductive material is electrically connected through the first interconnect structure to a ground point.

24. The semiconductor device of claim 21, further including:

a plurality of conductive vias formed through the first encapsulant;

a second interconnect structure formed over the first encapsulant;

a second semiconductor die mounted over the second interconnect structure; and

a second encapsulant deposited over the second semiconductor die, wherein the shielding layer is formed over the second encapsulant and the conductive material surrounds the first and second semiconductor die.

25. The semiconductor device of claim 21, further including

a plurality of conductive vias formed through the first encapsulant;

a second interconnect structure formed over the first encapsulant;

a second semiconductor die mounted over the first semiconductor die; and

a second encapsulant deposited over the second semiconductor die, wherein the shielding layer is formed over the second encapsulant and the conductive material surrounds only the second semiconductor die.