RAIL-TO-RAIL INPUT STAGE CIRCUIT WITH DYNAMIC BIAS CONTROL

• US 20110298541A1
• Filed: 06/08/2010
• Published: 12/08/2011
• Est. Priority Date: 06/08/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Shi, Chunlei
• Granted Patent: US 8,102,211 B2
• Time in Patent Office: Days
• US Class Current: 330/261
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45708 Controlling the common source circuit of the differential amplifier

Abstract

An improved rail-to-rail (R-R) input stage circuit with dynamic bias control is described. Input stage circuit includes a differential pair circuit, a level shifted differential pair and a bias control circuit. The differential pair circuit and the level shifted differential pair are of same type, non-complementary MOS devices. In exemplary embodiments, a first and a second bias control circuits dynamically control the bias current of the level shifted differential pair and the bias current of the differential pair circuit, respectively, in response to the input common mode voltage of the rail-to-rail input stage circuit. First and second bias control circuits maintain the output impedance of the R-R input stage circuit at a desired level, as the R-R input stage circuit operates outside the input common mode voltage range supported by the level shifted differential pair and the differential pair circuit, respectively. Further exemplary embodiments include a first and a second gm control circuits. Gm control circuits maintain the transconductance of the R-R input stage circuit substantially constant over the entire input common mode voltage range of the R-R input stage circuit.

Claims

1. A rail-to-rail (R-R) input stage circuit operating over a rail-to-rail input common mode voltage range, comprising:

a differential pair circuit, having a first input common mode voltage range, coupled to a level shifted differential pair, having a second input common mode voltage range to enable operation of the R-R input stage circuit over an input common mode voltage that extends from a negative power supply to a positive power supply; and

a first bias control circuit, coupled to the level shifted differential pair, to dynamically control the bias current of the level shifted differential pair when the input common mode voltage of the R-R input stage circuit is outside the second input common voltage range.

2. The R-R input stage circuit of claim 1, where the first bias control circuit gradually turns off the level shifted differential pair in response to the input common mode voltage of the R-R input stage circuit.

3. The R-R input stage circuit of claim 1, where the first bias control circuit further comprises a voltage sensor circuit for generating a tracking current inversely proportional to a sensed input common mode voltage of the R-R input stage, when the input common mode voltage of the R-R input stage circuit is outside the second input common voltage range.

4. The R-R input stage circuit of claim 3, further comprising a current mirror circuit having one terminal coupled to the voltage sensor circuit and a second terminal coupled to the current source of the level shifted differential pair to control the bias current of the level shifted differential pair in response to the tracking current.

5. The R-R input stage circuit of claim 3, where the voltage sensor circuit is a MOS device, and where the input common mode voltage of the R-R input stage circuit controls the gate of the MOS device.

6. The R-R input stage circuit of claim 4, where the current mirror comprises a MOS device, having its gate and drain coupled to the voltage sensor circuit and to the current source of the level shifted differential pair.

7. The R-R input stage circuit of claim 1, where the differential pair circuit comprises a pair of matched MOS transistors and a current source.

8. The R-R input stage circuit of claim 1, where the level shifted differential pair comprises a source follower and a differential pair circuit, where the differential pair circuit comprises a pair of matched MOS transistors and a current source.

9. The source follower of claim 8, comprising a pair of matched MOS transistors of type complementary to that of the MOS transistors of the differential pair circuit.

10. The R-R input stage circuit of claim 3, further comprising a second bias control circuit, coupled to the differential pair circuit, to dynamically control the bias current of the differential pair circuit when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.

11. The R-R input stage circuit of claim 10, where the second bias control circuit gradually turns off the differential pair circuit in response to the input common mode voltage of the R-R input stage circuit.

12. The R-R input stage circuit of claim 10, further comprising a first gm control circuit having a first terminal coupled to the first bias control circuit and a second terminal coupled to the current source of the differential pair circuit, where the first gm control circuit adjusts the current through the differential pair circuit to maintain the transconductance of the R-R input stage circuit substantially constant when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.

13. The R-R input stage circuit of claim 12, where the first gm control circuit adjusts the current through the differential pair circuit in response to the tracking current generated by the first bias control circuit.

14. The R-R input stage circuit of claim 13, further comprising a second gm control circuit having a first terminal coupled to the second bias control circuit and a second terminal coupled to the current source of the level shifted differential pair, where the second gm control circuit adjusts the current through the level-shifted differential pair to maintain substantially constant the transconductance of the R-R input stage circuit when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.

15. The R-R input stage circuit of claim 14, where the second gm control circuit adjusts the current through the level shifted differential pair in response to the tracking current generated by the second bias control circuit.

16. A rail-to-rail (R-R) input stage circuit operating over a rail-to-rail input common mode voltage range, comprising:

a differential pair circuit, having a first input common mode voltage range, coupled to a level shifted differential pair, having a second input common mode voltage range to enable operation of the R-R input stage circuit over an input common mode voltage that extends from negative power supply to positive power supply; and

first means, coupled to the level shifted differential pair, for dynamically controlling the bias current of the level shifted differential pair when the input common mode voltage of the R-R input stage circuit is outside of the second input common mode voltage range.

17. The R-R input stage circuit of claim 16, where the first means gradually turns off the level shifted differential pair in response to the input common mode voltage of the R-R input stage circuit.

18. The R-R input stage circuit of claim 16, where the first means includes means for sensing the input common mode voltage of the R-R input stage circuit.

19. The R-R input stage circuit of claim 18, where the means for sensing also generate a tracking current inversely proportional to the sensed input common mode voltage, when the input common mode voltage of the R-R input stage circuit is outside the second input common mode voltage range.

20. The R-R input stage circuit of claim 19, where the first means further comprises means for mirroring the tracking current to the current source of the level shifted differential pair to control the bias current of the level shifted differential pair.

21. The R-R input stage circuit of claim 19, further comprising second means coupled to the differential pair circuit, to dynamically control the bias current of the differential pair circuit when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.

22. The R-R input stage circuit of claim 21, where the second means gradually turns off the differential pair circuit in response to the input common mode voltage of the R-R input stage circuit.

23. The R-R input stage circuit of claim 22, where the second means includes means for sensing the input common mode voltage of the R-R input stage circuit.

24. The R-R input stage circuit of claim 23, where the means for sensing also generate a tracking current inversely proportional to the sensed input common mode voltage, when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.

25. The R-R input stage circuit of claim 19, further comprising first gm control means having a first terminal coupled to the first means and a second terminal coupled to the differential pair circuit, where the first gm control means adjusts the current through the differential pair circuit in response to the tracking current generated by the first means, to maintain the transconductance of the R-R input stage circuit substantially constant when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.

26. The R-R input stage circuit of claim 25, further comprising second gm control means having a first terminal coupled to the second means and a second terminal coupled to the level shifted differential pair, where the second gm control means adjust the current through the level shifted differential pair in response to the tracking current generated by the second means, to maintain the transconductance of the R-R input stage circuit substantially constant when the input common mode voltage of the R-R input stage circuit is outside the second input common mode voltage range.