TOUCH-DISPLAY CROSSTALK
First Claim
1. A method of clamping a circuit element of a touch screen to a predetermined voltage, the method comprising:
- during a touch sensing phase in which a touch is sensed, connecting the circuit element to a first source of the predetermined voltage; and
during a display phase in which an image is displayed on the touch screen, disconnecting the circuit element from the first source of the predetermined voltage.
1 Assignment
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Accused Products
Abstract
Clamping of a circuit element of a touch screen, such as a gate line of the display system of the touch screen, to a fixed voltage is provided. The circuit element can be clamped during a touch phase and unclamped during a display phase of the touch screen. A gate line system of a touch screen can include a first transistor with a source or drain connected to a first gate line, a second transistor with a source or drain connected to a second gate line, and a common conductive pathway connecting gates of the first and second transistors. A synchronization system can switch the first and second transistors to connect the first and second gate lines to a fixed voltage during a touch phase, and can switch the first and second transistors to disconnect the first and second gate lines from the fixed voltage during a display phase.
71 Citations
15 Claims
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1. A method of clamping a circuit element of a touch screen to a predetermined voltage, the method comprising:
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during a touch sensing phase in which a touch is sensed, connecting the circuit element to a first source of the predetermined voltage; and during a display phase in which an image is displayed on the touch screen, disconnecting the circuit element from the first source of the predetermined voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A gate line system of a touch screen, the gate line system comprising:
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a first transistor with a source or drain connected to a first gate line; a second transistor with a source or drain connected to a second gate line; and a common conductive pathway connecting gates of the first and second transistors. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification