INTEGRATED CIRCUIT HEATING TO EFFECT IN-SITU ANNEALING

• US 20110299317A1
• Filed: 08/19/2010
• Published: 12/08/2011
• Est. Priority Date: 11/29/2006
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Shaeffer, Ian P., Bronner, Gary B., Haukness, Brent S., Donnelly, Kevin S., Ware, Frederick A., Horowitz, Mark A.
• Granted Patent: US 8,344,475 B2
• Time in Patent Office: Days
• US Class Current: 365/106
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence

Abstract

In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.

Claims

1. A method of operating a system having a memory device, the method comprising:

detecting an event during operation of the system; and

heating the memory device to a threshold temperature to reverse use-incurred degradation of the memory device in response to detecting the event.

2. The method of claim 1 wherein detecting an event during operation of the system comprises determining that a predetermined time has been reached.

3. The method of claim 1 wherein detecting the event during operation of the system comprises determining that a predetermined amount of time has elapsed since detection of a prior event, wherein the memory device was previously heated to the threshold temperature in response to the prior event.

4. The method of claim 1 wherein detecting the event during operation of the system comprises determining that a threshold number of operations have been performed within the memory device.

5. The method of claim 4 wherein the threshold number of operations comprise programming operations in which electric charge is trapped within charge-trapping layers within respective memory cells of the memory device.

6. The method of claim 5 wherein the memory device comprises a flash memory device.

7. The method of claim 1 wherein detecting the event during operation of the system comprises determining that an error threshold has been reached in connection with operation of the memory device.

8. The method of claim 7 wherein determining that an error threshold has been reached comprises determining that a threshold bit-error rate has been reached with respect to data read from the memory device.

9. The method of claim 7 wherein determining that an error threshold has been reached comprises determining that a predetermined number of bad storage blocks have been detected.

10. The method of claim 1 wherein detecting the event during operation of the system comprises detecting occurrence of an event specified by programmable register within the system.

11. The method of claim 9 further comprising storing a specification of the event within the programmable register in response to input from a human operator.

12. The method of claim 11 wherein the memory device is a first memory device of a plurality of memory devices within the system, and wherein the method comprises executing a memory access within at least one memory device of the plurality of memory devices other than the first memory device while heating the first memory device to the threshold temperature.

13. The method of claim 12 wherein executing a memory access comprises reading data from the at least one memory device.

14. The method of claim 12 wherein executing a memory access comprises writing data to the at least one memory device.

15. The method of claim 1 wherein the memory device is a first memory device of a plurality of memory devices within the system, the method further comprising evacuating data from the first memory device to at least one other memory device of the plurality of memory devices prior to heating the first memory device to the threshold temperature.

16. The method of claim 15 wherein evacuating data from the first memory device to the at least one other memory device comprises establishing within the at least one other memory device a copy of all valid data in the first memory device.

17. The method of claim 16 wherein evacuating data from the first memory device to at least one other memory device of the plurality of memory devices comprises evacuating data from the first memory device to the at least one other memory device and to at least a second other memory device of the plurality of memory devices.

156. The method of claim 1 wherein detecting the event during operation of the system comprises determining that the system has been coupled to an external power source.

18. A data storage system comprising:

a memory device; and

control circuitry to detect, during operation of the data storage system, an event indicating a need to counteract use-related degradation of the memory device and, in response to detecting the event, to heat the memory device to counteract the use-related degradation.

19. The data storage system of claim 18 wherein the memory device comprises non-volatile storage cells that exhibit, as an aspect of use-related degradation, progressively degraded data retention times as programming operations are executed to stored data within the non-volatile storage cells.

20. The data storage system of claim 18 wherein the circuitry to detect an event indicating a need to counteract use-related degradation comprises circuitry to detect that a threshold number of performance-degrading operations have been executed within the memory device.

21. The data storage system of claim 20 wherein the circuitry to detect that a threshold number of performance-degrading operations have been executed comprises a programmable register and circuitry to store a value indicative of the threshold number of performance-degrading operations within the programmable register upon receiving the value from a source external to the data storage system.

22. The data storage system of claim 18 wherein the circuitry to detect an event indicating a need to counteract use-related degradation comprises circuitry to determine that a threshold quantity of errors have been detected during operation of the memory device.

23. The data storage system of claim 22 wherein the circuitry to determine that a threshold quantity of errors have been detected during operation of the memory device comprises circuitry to determine that a threshold quantity of errors have been detected within a time interval and therefore to determine that a threshold error rate has been reached.

24. The data storage system of claim 22 wherein the circuitry to determine that a threshold quantity of errors have been detected comprises circuitry to detect that a threshold number of unreliable storage regions have been identified within the memory device.

25. The data storage system of claim 22 wherein the circuitry to determine that a threshold quantity of errors have been detected comprises circuitry to detect that a threshold number of data programming operations within the memory device have been unsuccessful.

26. The data storage system of claim 22 wherein the circuitry to determine that a threshold quantity of errors have been detected comprises circuitry to detect that threshold number of bit errors are present within data retrieved from the memory device.

27. The data storage system of claim 18 wherein the circuitry to heat the memory device to counteract the use-related degradation comprises heating circuitry disposed in proximity to the memory device.

28. The data storage system of claim 27 further comprising a packaging structure and wherein the memory device comprises an integrated-circuit die disposed within the packaging structure and wherein the heating structure is disposed within the packaging structure adjacent the integrated-circuit die.

29. The data storage system of claim 27 further comprising a printed circuit board and wherein the heating circuitry and memory device are mounted proximally to one another on the printed circuit board.

30. The data storage system of claim 27 wherein the memory device and heating circuitry are integrated within an integrated circuit die.

31. The data storage system of claim 30 wherein the memory device comprises data storage and retrieval circuitry to enable data storage and retrieval operations within the memory device, and wherein one or more conductive structures that form part of the data storage and retrieval circuitry also form part of the heating circuitry.

32. The data storage system of claim 18 wherein the control circuitry comprises data-evacuation circuitry to evacuate data from the memory device prior to heating the memory device.

33. The data storage system of claim 32 wherein the memory device constitutes a first memory device of a plurality of memory devices comprised by the data storage system, and wherein the data-evacuation circuitry comprises circuitry to evacuate data from the first memory device to one or more other memory devices of the plurality of memory devices prior to heating the first memory device.

34. The data storage system of claim 32 wherein the memory device constitutes a first memory device of a plurality of memory devices comprised by the data storage system, and wherein the data-evacuation circuitry comprises circuitry to evacuate data from the first memory device to a second memory device of the plurality of memory devices in a sequence of evacuation stages, the evacuation stages including a passive evacuation stage in which previously stored data within the first memory device is invalidated by re-directing data otherwise to be stored within the first memory device as a substitute for the previously stored data to the second storage device.

35. The data storage system of claim 34 wherein the evacuation stages implemented by the circuitry to evacuate data in a sequence of stages further includes an active evacuation stage in which the data-evacuation circuitry copies data previously stored within the first memory device to the second memory device.

36. The data storage system of claim 35 wherein the control circuitry comprises a page table to indicate storage locations of pages of data within the plurality of memory devices, and wherein the circuitry to evacuate data in a sequence of stages comprises circuitry to update the page table during the active evacuation stage to specify the second memory device as the repository of the data previously stored within first memory device.

37. The data storage system of claim 18 wherein the memory device constitutes a first memory device of the data storage system and wherein the data storage system further comprises:

a second memory device which, together with the first memory device, constitutes at least part of a memory subsystem of the data storage system; and

circuitry to perform a data access operation within the second memory device during an interval over which the first memory device is being heated by the control circuitry to counteract the use-related degradation thereof.

157. The data storage system of claim 18 wherein the circuitry to detect an event indicating a need to counteract use-related degradation comprises circuitry to detect that the data storage system has been coupled to an external power source.

38-154. -154. (canceled)

155. A data storage system comprising:

a memory device;

means for detecting an event during operation of the data storage system; and

means for heating the memory device to a threshold temperature to reverse use-incurred degradation of the memory device in response to detecting the event.