METHODS AND APPARATUS FOR AN ISFET

• US 20110299337A1
• Filed: 06/04/2010
• Published: 12/08/2011
• Est. Priority Date: 06/04/2010
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Parris, Patrice M., Chen, Weize, De Souza, Richard J., McKenna, John M., Hoque, Md M.
• Granted Patent: US 8,878,257 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

Claims

1. An ISFET structure comprising:

a substrate;

a source region and a drain region formed within the substrate and having a channel region provided therebetween;

a gate dielectric layer formed over the channel region;

a floating gate structure formed on the gate dielectric over the channel region, the floating gate structure being electrically coupled to a first conductive structure configured to electrically communicate with a fluid having an ion concentration; and

at least one control gate structure electrically coupled to the floating gate structure, the control gate structure configured to accept a voltage bias and to cause the movement of charge between the floating gate structure and the control gate structure in response to the voltage bias.

2. The ISFET structure of claim 1, wherein the at least one control gate structure comprises a control gate electrode and a capacitor structure formed by the substrate, the floating gate, and an oxide layer provided therebetween.

3. The ISFET structure of claim 2, wherein the capacitor structure is formed between the floating gate and a well provided within the substrate.

5. The ISFET structure of claim 1, further including at least one metal-insulator-metal capacitor coupled between the floating gate structure and the first conductive structure.

6. The ISFET structure of claim 1, wherein the floating gate structure comprises polysilicon.

4. The ISFET structure of 1, wherein the at least one control gate includes two control gates, each forming a respective capacitor in conjunction with the substrate.

7. A method of trimming the threshold voltage of an ISFET having a floating gate and a control gate coupled thereto, comprising;

determining a first threshold voltage value of the ISFET;

applying a bias voltage to the control gate based on the first threshold voltage such that at least a portion of charge within the ISFET migrates to or from the control gate;

adjusting the bias voltage until the ISFET has a second threshold voltage substantially equal to a predetermined threshold value; and

removing the bias voltage from the control gate.

8. The method of claim 7, wherein the control gate includes a first control gate terminal and a second control gate terminal, and the applying step includes applying a positive voltage to either the first control gate terminal or the second control gate terminal.

9. The method of claim 7, wherein applying the bias voltage to the control gate includes applying the bias voltage across a capacitor structure formed in part by the substrate, the floating gate, and a dielectric layer provided therebetween.

10. The method of claim 9, wherein applying the bias voltage includes applying the bias voltage between a capacitor structure formed by a well formed in the substrate, the floating gate, and the dielectric layer.

11. The method of claim 9, wherein applying the bias voltage includes applying the bias voltage across at least one metal-insulator-metal capacitor coupled between the floating gate structure and the first conductive structure.

12. The method of claim 9, wherein applying the bias voltage includes applying the bias voltage to one of two control gates, each comprising a capacitor structure formed in part by the substrate.

13. A method of forming a CMOS ISFET, comprising:

providing a substrate;

forming a floating gate structure over the substrate; and

forming a control gate structure communicatively coupled to the floating gate structure, such that the control gate is configured to receive a bias voltage and effect transfer of charge selectively between the floating gate structure and the control gate structure.

14. The method of claim 13, wherein the control gate structure comprises a control gate electrode and a capacitor structure formed by the substrate, the floating gate, and an oxide layer provided therebetween.

15. The method of claim 14, wherein the capacitor structure is formed between the floating gate and a well provided within the substrate.

16. The method of claim 13, wherein the control gate structure includes two control gates, each forming a respective capacitor with the substrate.

17. The method of claim 13, further including forming at least one metal-insulator-metal capacitor coupled between the floating gate structure and the first conductive structure.

18. The method of claim 13, wherein forming the floating gate structure includes forming a polysilicon structure.

19. The method of claim 15, wherein the well comprises an n-type impurity diffusion region.

20. The method of claim 13, wherein the floating gate structure includes a metal plate configured to sense an ion concentration of a fluid adjacent thereto.