SYSTEMS AND METHODS FOR PROVIDING INSTANT-ON FUNCTIONALITY ON AN EMBEDDED CONTROLLER

• US 20110302343A1
• Filed: 06/03/2010
• Published: 12/08/2011
• Est. Priority Date: 06/03/2010
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Maddukuri, Akkiah, Jreij, Elie, Butcher, Wade
• Granted Patent: US 8,819,321 B2
• Time in Patent Office: Days
• US Class Current: 710/107
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

Systems and methods for providing instant-on functionality on an embedded controller are disclosed. A method of providing instant-on functionality on a controller comprises an initial state, an intermediate state and a final state. The initial state comprises installing a first responder code, enabling the first responder code and enabling a timer interrupt service routine. The intermediate state comprises registering the first responder code as a timer interrupt service routine. The timer interrupt service routine initiates periodic processing. The final state comprises registering a steady-state interrupt service routine.

Claims

1. A method of providing instant-on functionality on a controller comprising:

an initial state;

wherein the initial state comprises;

installing a first responder code;

enabling the first responder code; and

enabling a timer interrupt service routine;

an intermediate state;

wherein the intermediate state comprises;

registering the first responder code as a timer interrupt service routine;

wherein the timer interrupt service routine initiates periodic processing; and

a final state;

wherein the final state comprises registering a steady-state interrupt service routine.

2. The method of claim 1, wherein the first responder code, the timer interrupt service routine and a bootloader are installed in a pre-allocated area of Random Access Memory.

3. The method of claim 2, wherein the pre-allocated area of Random Access Memory survives transition to the Operating System.

4. The method of claim 1, wherein the first responder code becomes an initial vector address for handling timer interrupt service routines.

5. The method of claim 1, further comprising mapping the first responder code in an address space of an Operating System application.

6. The method of claim 1, wherein the Operating System interrupt handler is stored in a pre-allocated area of Random Access Memory.

7. The method of claim 1, wherein the controller is part of a remotely controlled interface card.

8. The method of claim 7, wherein the remotely controlled interface card is an Integrated Remote Access Controller.

9. The method of claim 1, wherein in the final state, the Operating System is fully booted.

10. The method of claim 1, wherein in the intermediate state, an Operating System interrupt handler registers the first responder code as a timer interrupt service routine.

11. The method of claim 1, wherein in the final state, an Operating System registers the steady-state interrupt service routine.

12. The method of claim 1, wherein the controller is an embedded controller.

13. The method of claim 1, wherein in the final state, the Operating System takes control of a Keyboard Controller Style bus.

14. An information handling system comprising:

a power source; and

a motherboard powered by the power source;

wherein the motherboard comprises;

an embedded processor;

a memory segment; and

a network connection;

wherein the memory segment comprises;

a first segment comprising;

a first responder micro-application;

a timer interrupt service routine; and

a boot loader;

a second segment comprising an interrupt handler; and

a third segment comprising;

an intelligent platform management interface stack;

a web server; and

an operating system application.

15. The information handling system of claim 14, wherein at least one of the first segment and the second segment is a Random Access Memory.

16. The information handling system of claim 14, wherein the first responder micro application interfaces with a host processor.

17. The information handling system of claim 16, wherein the first responder micro application interfaces with the host processor though a low pin count bus.

18. The information handling system of claim 14, wherein the embedded processor is an integrated remote access controller.

19. The information handling system of claim 14, wherein the second segment is a kernel space random access memory.