SYSTEMS AND METHODS FOR RELIABLE MULTI-LEVEL CELL FLASH STORAGE

• US 20110302354A1
• Filed: 06/02/2010
• Published: 12/08/2011
• Est. Priority Date: 06/02/2010
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Miller, Mark E.
• Granted Patent: US 8,301,828 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Multi-level cell (MLC) flash memory has become widely used due to their capacity to store more information in the same area as a single-level cell (SLC) flash memory. This makes MLC flash memory very attractive for storing media. Flash has also traditionally been used in electronic devices for firmware, but MLC flash is less reliable than SLC flash. For critical memory operations, MLC flash memory can be made as reliable as SLC flash by mapping one binary value to an MLC state corresponding to the highest threshold voltage and the other binary value to the MLC state corresponding the lowest threshold voltage when writing to the MLC flash, and by mapping all MLC states with corresponding threshold voltages above a central cutoff threshold voltage to one binary value and by mapping all MLC states with corresponding threshold voltages below a central cutoff threshold voltage to the other binary value.

Claims

1. An electronic device comprising:

a processing unit;

a multi-level cell (MLC) flash memory comprising a plurality of multi-level memory cells comprising a plurality of MLC states, the MLC flash memory comprising a critical portion; and

a memory controller interfacing the MLC flash with the processing unit, the memory controller responsive to read instructions from the processing unit to read a binary value from an MLC state stored in a given multi-level memory cell in the critical portion.

2. The electronic device of claim 1, wherein the MLC flash memory further comprises a non-critical portion;

and

the memory controller responsive to read instructions from the processing unit to read multiple bits of data from an MLC state stored in a given multi-level memory cell.

3. The electronic device of claim 1 wherein each MLC state has an associated threshold voltage;

wherein the memory controller reads a first binary value from a given multi level memory cell whenever the given multi level memory cell is in a MLC state having a threshold voltage greater than a cutoff threshold voltage and a second binary value whenever the given multi level memory cell is in a MLC state having threshold voltage less than a cutoff threshold voltage.

4. The electronic device of claim 1 wherein the MLC flash is a 2-bit per cell (2BPC) flash memory and the plurality of MLC states comprises a 00 state, a 01 state, a 10 state and a 11 state, and the memory controller reads a first binary value from a given multi level memory cell whenever the given multi level memory cell is in the 10 state or the 11 state and a second binary value whenever the given multi level memory cell is in the 00 state or the 01 state.

5. The electronic device of claim 1 wherein the MLC flash is a 3-bit per cell (3BPC) flash memory and the plurality of MLC states comprises a 000 state, a 001 state, a 010, a 011 state, 100 state, a 101 state, a 110 state and a 111 state, and the memory controller reads a first binary value from a given multi level memory cell whenever the given multi level memory cell is in the 100 state, the 101 state, the 110 state or the 111 state and a second binary value whenever the given multi level memory cell is in the 000 state, the 001 state, the 010 state or the 011 state.

6. The electronic device of claim 1 wherein the MLC flash is a 4-bit per cell (4BPC) flash memory and the plurality of MLC states comprises a 0000 state, a 0001 state, a 0010, a 0011 state, 0100 state, a 0101 state, a 0110 state, a 0111 state, a 1000 state, a 1001 state, a 1010, a 1011 state, 1100 state, a 1101 state, a 1110 state and a 1111 state, and the memory controller reads a first binary value from a given multi level memory cell whenever the given multi level memory cell is in the 1000 state, the 1001 state, the 1010 state, the 1011 state, the 1100 state, the 1101 state, the 1110 state or the 1111 state and a second binary value whenever the given multi level memory cell is in the 0000 state, the 0001 state, the 0010 state, 0011 state, the 0100 state, the 0101 state, the 0110 state or the 0111 state.

7. The electronic device of claim 2, wherein the memory controller responsive to write instructions from the processor stores MLC data into the critical portion where the MLC data comprises only a high MLC value corresponding to a lowest threshold voltage and/or a low MLC value and/or a low MLC value corresponding to a highest threshold voltage.

8. The electronic device of claim 2, wherein the memory controller responsive to write instructions from the processor writes data comprising a first binary value and a second binary value into the critical portion by storing a highest MLC state whenever an instruction to write a first binary value is encountered and by storing a lowest MLC state whenever an instruction to write a second binary value is encountered.

9. The electronic device of claim 8, wherein the MLC flash memory is a 2BPC flash memory and a 11 MLC state is the highest MLC state and a 00 MLC state is the lowest MLC state.

10. The electronic device of claim 8, wherein the MLC flash memory is a 3BPC flash memory and a 111 MLC state is the highest MLC state and a 000 MLC state is the lowest MLC state.

11. The electronic device of claim 5, wherein the MLC flash memory is a 4BPC flash memory and a 1111 MLC state is the highest MLC state and a 0000 MLC state is the lowest MLC state.

12. The electronic device of claim 8 wherein the MLC flash memory is a Gray coded 2BPC flash memory and a 10 MLC state is the highest MLC state and a 00 MLC state is the lowest MLC state.

13. The electronic device of claim 8, wherein the wherein the MLC flash memory is a Gray coded 2BPC flash memory and a 100 MLC state is the highest MLC state and a 000 MLC state is the lowest MLC state.

14. The electronic device of claim 2, wherein the critical portion comprises a static critical portion and a dynamic critical portion;

wherein the memory controller responsive to write instructions from the processor stores MLC data into the static critical portion where the MLC data comprises only a high MLC value corresponding to a highest MLC state and/or a low MLC value corresponding to the lowest MLC state; and

responsive to write instructions from the processor writes data comprising a first binary value and a second binary value into the dynamic critical portion by storing a highest MLC state whenever an instruction to write a first binary value is encountered and by storing a lowest MLC state whenever an instruction to write a second binary value is encountered.

15. The electronic device of claim 1, wherein the electronic device is a digital camera, a printer, a multi-function peripheral, a scanner, a music player, a portable video game, a camcorder, a digital picture frame, a cellular telephone, or a combination thereof.

26. The MLC flash cell of claim 10, wherein the MLC flash cell is a 3BPC flash cell and a 111 MLC state is the highest MLC state and a 000 MLC state is the lowest MLC state.

27. The MLC flash cell of claim 10, wherein the MLC flash memory is a 4BPC flash cell and a 1111 MLC state is the highest MLC state and a 0000 MLC state is the lowest MLC state.

16. A MLC flash memory comprising:

a critical portion and a non-critical portion, each portion comprising a plurality of memory cells;

wherein data stored in each memory cell in the non-critical portion is stored in one of a plurality of MLC states, said plurality including a highest MLC state and a lowest MLC state; and

wherein data stored in each memory cell in the critical portion is stored in either the highest MLC state or the lowest MLC state.

17. The MLC flash memory of claim 16, wherein the MLC flash memory is 2BPC flash memory and a 11 MLC state is the highest MLC state and a 00 MLC state is the lowest MLC state.

18. The MLC flash memory of claim 16, wherein the MLC flash memory is a 3BPC flash memory and a 111 MLC state is the highest MLC state and a 000 MLC state is the lowest MLC state.

19. The MLC flash memory of claim 16, wherein the MLC flash memory is a 4BPC flash memory and a 1111 MLC state is the highest MLC state and a 0000 MLC state is the lowest MLC state.

22. The method of claim 17, wherein the data unit is selected from the group consisting of a byte, a word, a double word, and a block.

20. A method of reading multi-level cell (MLC) flash memory having a critical portion and a non-critical portion comprising:

receiving a memory address;

reading data at the memory address;

determining whether the memory address is in the critical portion;

if the memory address is in the critical portion, assigning a binary value to each MLC state read from the data stored at the memory address.

wherein a first binary value is assigned if the MLC state read has an associated threshold voltage greater than a central cutoff threshold voltage and a second binary value is assigned if the MLC state read has an associated threshold voltage less than a central cutoff threshold voltage.

21. The method of claim 20, wherein the flash memory is a b-bits per cell flash, said method further comprising:

obtaining a physical address from the memory address using a logical to physical mapping; and

wherein reading the data at the memory address comprises reading a data unit if the memory address is in the non-critical portion and reading b data units in the critical portion.

23. A method of storing binary value into an MLC flash cell comprising:

programming a MLC state corresponding to a highest threshold voltage if the binary value is a first binary value;

programming a MLC state corresponding to a lowest threshold voltage if the binary value is a second binary value.

24. The method of claim 23, wherein the first binary value is a 1 and the second binary value is a 0.

25. The method of claim 23, wherein the MLC flash cell is a 2BPC flash cell and a 11 MLC state is the highest MLC state and a 00 MLC state is the lowest MLC state.