SEMICONDUCTOR ARRANGEMENT AND METHOD OF PRODUCING A SEMICONDUCTOR ARRANGEMENT

• US 20110303945A1
• Filed: 01/29/2010
• Published: 12/15/2011
• Est. Priority Date: 02/12/2009
• Status: Active Grant

• Current Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: Zitzlsperger, Michael, Sperl, Matthias
• Granted Patent: US 8,710,609 B2
• Time in Patent Office: Days
• US Class Current: 257/99
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49586 Insulating layers on lead frames
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/54 : having a particular shape
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A semiconductor arrangement including at least one lead arrangement with a top and a bottom opposite the top; a least one solder resist layer which partially covers the top and the bottom, at least sub-zones of the top and the bottom, which are not covered by the solder resist layer, forming electrical base members; an optoelectronic semiconductor element, which is mounted on at least one of the base members on the top of the lead arrangement and is connected electrically conductively therewith, and an encapsulant applied at least to the top of the lead arrangement, the encapsulant covering up the semiconductor element and lying at least partially against the solder resist layer, wherein the base members are bordered all round by the solder resist layer.

Claims

1-15. -15. (canceled)

16. A semiconductor arrangement comprising:

at least one lead arrangement with a top and a bottom opposite the top;

at least one solder resist layer which partially covers the top and the bottom, at least sub-zones of the top and the bottom, which are not covered by the solder resist layer, forming electrical base members;

an optoelectronic semiconductor element, which is mounted on at least one of the base members on the top of the lead arrangement and is connected electrically conductively therewith, and

an encapsulant applied at least to the top of the lead arrangement, the encapsulant covering up the semiconductor element and lying at least partially against the solder resist layer,

wherein the base members are bordered all round by the solder resist layer.

17. The semiconductor arrangement according to claim 16, wherein the lead arrangement comprises at least one well in which the semiconductor element is secured.

18. The semiconductor arrangement according to claim 16, wherein the base members of the bottom are not covered by the encapsulant.

19. The semiconductor arrangement according to claim 16, in which the lead arrangement comprises at least two mutually electrically insulated portions, herein the semiconductor element is mounted on one of the portions and connected electrically conductively via an electrically conductive connecting element to at least one other of the portions.

20. The semiconductor arrangement according to claim 19, wherein the at least two portions are separated from one another by a slit.

21. The semiconductor arrangement according to claim 16, wherein the lead arrangement is made from a sheet metal semi-finished product or in which the lead arrangement is made from a semi-finished product of plastic material, the base members being arranged on both sides thereof.

22. The semiconductor arrangement according to claim 16, wherein the solder resist layer is of U-shaped crosssection at least in selected locations, such that the solder resist layer extends beyond end faces of the lead arrangement and reaches as a continuous layer from the top to the bottom.

23. The semiconductor arrangement according to claim 16, wherein the solder resist layer consists of a solder resist lacquer.

24. The semiconductor arrangement according to claim 16, comprising at least two of the base members both on the top and on the bottom.

25. The semiconductor arrangement according to claim 20, in which the connecting element is a bonding wire.

26. The semiconductor arrangement according to claim 16, wherein the at least one semiconductor element is a light-emitting diode, a laser diode or a photodiode.

27. A method of producing a semiconductor arrangement comprising:

providing a lead arrangement with a top and a bottom opposite thereto,

at least partially applying at least one solder resist layer to the top and the bottom of the lead arrangement, at least sub-zones of the top and the bottom, which are not covered by the solder resist layer, forming electrical base members,

arranging an optoelectronic semiconductor element on one of the base members on the top of the lead arrangement such that the element is connected electrically conductively to the lead arrangement, and

encapsulating the semiconductor component in such a way on the lead arrangement with an encapsulant that the encapsulant is at least partially in mechanical contact with the solder resist layer, wherein

the base members are bordered all around by the solder resist layer.

28. The method according to claim 27, wherein the lead arrangement is provided as pan of a sheet metal semi-finished product and the solder resist layer is applied before the lead arrangement is separated from the semi-finished product.

29. The method according to claim 27, wherein after application of the solder resist layer, the base members are each provided with at least one metallic layer, wherein regions of the top and the bottom covered by the solder resist layer remain uncovered by the metallic layer.

30. The method according to claim 27, wherein the solder resist layer is applied in a patterned manner and cured and/or dried, wherein after curing or drying the solder resist layer remains complete on the top and bottom of the lead arrangement.