SEMICONDUCTOR DEVICE AND PRODUCTION METHOD

• US 20110303973A1
• Filed: 05/26/2011
• Published: 12/15/2011
• Est. Priority Date: 06/15/2010
• Status: Active Grant

• Current Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Original Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Inventors: Masuoka, Fujio, Nakamura, Hiroki, Arai, Shintaro, Kudo, Tomohiko, Li, Xiang, Bliznetsov, Vladimir, Buddharaju, Kavitha Devi, Singh, Navab, Chui, King-Jien, Li, Yisuo, Jiang, Yu, Chen, Zhixian, Shen, Nansheng
• Granted Patent: US 9,153,697 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.

Claims

1. A semiconductor device provided with:

a first planar semiconductor layer;

a first columnar semiconductor layer formed on the first planar semiconductor layer;

a first high concentration semiconductor layer formed on the first planar semiconductor layer and the lower region of the first columnar semiconductor layer;

a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer, formed on the upper region of the first columnar semiconductor layer;

a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;

a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;

a first semiconductor film formed on the first metal film so as to surround the first metal film;

a first gate electrode composed of the first metal film and the first semiconductor film;

a first insulating film formed between the first gate electrode and the first planar semiconductor layer;

a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround the upper region of the first columnar semiconductor layer;

a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;

a first contact formed above the first columnar semiconductor layer;

a second contact formed above the first planar semiconductor layer; and

a third contact formed above the first gate electrode;

wherein the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film.

2. The semiconductor device according to claim 1, wherein the thickness of the second insulating film is thicker than the sum of the thickness of the first gate insulating film and the thickness of the first metal film.

3. The semiconductor device according to claim 1, further comprising a first metal-semiconductor compound formed on the upper surface of the first high concentration semiconductor layer.

4. The semiconductor device according to claim 1, wherein the length from the center of the first columnar semiconductor layer to the edge of the first planar semiconductor layer is larger than the sum of the length from the center to the sidewall of the first columnar semiconductor layer, the thickness of the first gate insulating film, the thickness of the first gate electrode and the thickness of the third insulating film.

5. The semiconductor device according to claim 1, further comprising a third metal-semiconductor compound formed on the top surface of the first gate electrode.

6. The semiconductor device according to claim 1, further comprising a second metal-semiconductor compound formed on the top surface of the second high concentration semiconductor layer.

12. A semiconductor device production method, being a method of producing the semiconductor device according to claim 1 and comprising:

a process for preparing a first structure having;

a first planar semiconductor layer;

a first columnar semiconductor layer formed on the first planar semiconductor layer and a hard mask formed on the top surface of the first columnar semiconductor;

a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer; and

a first insulating film formed on the first planar semiconductor layer;

a process for forming a seventh insulating film, a third metal film and a third semiconductor film, in that order, on the first structure;

a process for etching the third semiconductor film and leaving a sidewall shape on the sidewall on the first columnar semiconductor layer;

a process for etching the third metal film and leaving a sidewall shape on the sidewall of the first columnar semiconductor layer;

a seventh insulating film etching process for etching the seventh insulating film and leaving a sidewall shape on the sidewall of the first columnar semiconductor layer; and

a fourth semiconductor film formation process for forming a fourth semiconductor film on the result of the seventh insulating film etching process.

13. The semiconductor device production method according to claim 12, further comprising:

a process for planarizing the fourth semiconductor film and the third semiconductor film in the result of the fourth semiconductor film formation process and exposing the upper region of the first metal film;

a first metal film and first gate insulating film formation process for etching the third metal film and the seventh insulating film so that the upper sidewall of the first columnar semiconductor layer is exposed to form the first metal film and the first gate insulating film; and

,

a process for forming a first oxide film on the result of the first metal film and first gate insulating film formation process.

14. A semiconductor device production method, being a method of producing the semiconductor device according to claim 1 and comprising:

a process for preparing a second structure having;

a first planar semiconductor layer;

a first columnar semiconductor layer formed on the first planar semiconductor layer;

a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;

a first gate insulating film formed on the sidewall in the middle region of the first columnar semiconductor layer so as to surround the first columnar semiconductor layer;

a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;

a first semiconductor film formed on the first metal film so as to surround the first metal film;

a first gate electrode composed of the first metal film and the first semiconductor film; and

a first insulating film formed between the first gate electrode and the first planar semiconductor layer; and

a process for forming a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer on the upper region of the first columnar semiconductor layer on the second structure by injecting a dopant at an angle of 10 degrees to 60 degrees, with a line orthogonal to the substrate being 0 degrees.

15. A semiconductor device production method, being a method of producing the semiconductor device according to claim 1 and comprising:

a process for preparing a third structure having;

a first planar semiconductor layer;

a first columnar semiconductor layer formed on the first planar semiconductor layer;

a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;

a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer, formed on the upper region of the first columnar semiconductor layer;

a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;

a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;

a first semiconductor film formed on the first metal film so as to surround the first metal film;

a first gate electrode composed of the first metal film and the first semiconductor film; and

a first insulating film formed between the first gate electrode and the first planar semiconductor layer;

a process for forming an eighth insulating film on the third structure; and

a process for forming a second insulating film by etching the eighth insulating film in a sidewall shape so the eighth insulating film remains on the top surface of the first gate electrode and the upper sidewall of the first columnar semiconductor layer.

16. A semiconductor device production method, being a method of producing the semiconductor device according to claim 1 and comprising:

a process for preparing a fourth structure having;

a first planar semiconductor layer;

a first columnar semiconductor layer formed on the first planar semiconductor layer;

a first high concentration semiconductor layer formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;

a second high concentration semiconductor layer of the same conductive type as the first high concentration semiconductor layer, formed on the upper region of the first columnar semiconductor layer;

a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;

a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;

a first semiconductor film formed on the first metal film so as to surround the first metal film;

a first gate electrode composed of the first metal film and the first semiconductor film;

a first insulating film formed between the first gate electrode and the first planar semiconductor layer;

a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround the top region of the first columnar semiconductor layer;

a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film; and

a first gate wire connected to the first gate electrode;

a contact stopper formation process for forming a contact stopper on the fourth structure;

a process for forming an interlayer insulating film so as to bury the result of the contact stopper formation process;

a process for forming a first resist on the interlayer insulating film, excluding on top of the first columnar semiconductor layer;

a process for etching the interlayer insulating film and forming a first contact hole on the interlayer insulating film;

a first resist removal process for removing the first resist;

a process for forming a second resist on the result of the first resist removal process, excluding on the first planar semiconductor layer and on the first gate wire;

a process for etching the interlayer insulating film and forming a second contact hole on top of the first planar semiconductor layer and forming a third contact hole on top of the first gate wire, on the interlayer insulating film;

a process for removing the second resist; and

a process for forming a first contact positioned above the first columnar semiconductor layer, a second contact positioned above the first planar semiconductor layer and a third contact positioned above the first gate wire on the first contact hole, the second contact hole and the third contact hole, respectively.

7. A semiconductor device comprising a first transistor and a second transistor, wherein:

the first transistor comprises;

a first planar semiconductor layer;

a first columnar semiconductor layer formed on the first planar semiconductor layer;

a first high concentration semiconductor layer of second conductive type formed on the lower region of the first columnar semiconductor layer and on the region of the first planar semiconductor layer below the first columnar semiconductor layer;

a second high concentration semiconductor layer of second conductive type formed on the upper region of the first columnar semiconductor layer;

a first gate insulating film formed on the sidewall of the first columnar semiconductor layer between the first high concentration semiconductor layer and the second high concentration semiconductor layer, so as to surround the first columnar semiconductor layer;

a first metal film formed on the first gate insulating film so as to surround the first gate insulating film;

a first semiconductor film formed on the first metal film so as to surround the first metal film;

a first gate electrode composed of the first metal film and the first semiconductor film;

a first insulating film formed between the first gate electrode and the first planar semiconductor layer;

a second insulating film formed in sidewall shape contacting the upper sidewall of the first columnar semiconductor layer and the top surface of the first gate electrode so as to surround both regions of the first columnar semiconductor layer;

a third insulating film formed in a sidewall shape contacting the sidewall of the first insulating film and the first gate electrode so as to surround the first gate electrode and the first insulating film;

a first metal-semiconductor compound formed on the top surface of the portion of the first high concentration semiconductor layer formed in the region below the first columnar semiconductor layer;

a third metal-semiconductor compound formed on the top surface of the first gate electrode; and

,

a second metal-semiconductor compound formed on the top surface of the second high concentration semiconductor layer;

and the second transistor comprises;

a second planar semiconductor layer;

a second columnar semiconductor layer formed on the second planar semiconductor layer;

a third high concentration semiconductor layer of first conductive type formed on the lower region of the second columnar semiconductor layer and on the region of the second planar semiconductor layer below the second columnar semiconductor layer;

a fourth high concentration semiconductor layer of first conductive type formed on the upper region of the second columnar semiconductor layer;

a second gate insulating film formed on the sidewall of the second columnar semiconductor layer between the third high concentration semiconductor layer and the fourth high concentration semiconductor layer, so as to surround the second columnar semiconductor layer;

a second metal film formed on the second gate insulating film so as to surround the second gate insulating film;

a second semiconductor film formed on the second metal film so as to surround the second metal film;

a second gate electrode composed of the second metal film and the second semiconductor film;

a fourth insulating film formed between the second gate electrode and the second planar semiconductor layer;

a fifth insulating film formed in sidewall shape contacting the upper sidewall of the second columnar semiconductor layer and the top surface of the second gate electrode so as to surround the top region of the second columnar semiconductor layer;

a sixth insulating film formed in a sidewall shape contacting the sidewall of the fourth insulating film and the second gate electrode so as to surround the second gate electrode and the fourth insulating film;

a fourth metal-semiconductor compound formed on the top surface of the portion of the third high concentration semiconductor layer formed in the region below the second columnar semiconductor layer;

a fifth metal-semiconductor compound formed on the top surface of the second gate electrode; and

,

a sixth metal-semiconductor compound formed on the top surface of the fourth high concentration semiconductor layer;

wherein the first gate insulating film and the first metal film are covered by the first columnar semiconductor layer, the first semiconductor film, the first insulating film and the second insulating film, and

the second gate insulating film and the second metal film are covered by the second columnar semiconductor layer, the second semiconductor film, the fourth insulating film and the fifth insulating film.

8. The semiconductor device according to claim 7, wherein the first gate insulating film and the first metal film are formed from materials that make the first transistor enhancement-type, and

the second gate insulating film and the second metal film are formed from materials that make the second transistor enhancement-type.

9. The semiconductor device according to claim 7, wherein the thickness of the second insulating film is thicker than the sum of the thickness of the first gate insulating film and the thickness of the first metal film.

10. The semiconductor device according to claim 7, wherein the length from the center of the first columnar semiconductor layer to the edge of the first planar semiconductor layer is larger than the sum of the length from the center to the sidewall of the first columnar semiconductor layer, the thickness of the first gate insulating film, the thickness of the first gate electrode and the thickness of the third insulating film.

11. The semiconductor device according to claim 7, wherein:

the first conductive type is n+ type,

the second conductive type is p+ type, and

the first and second columnar semiconductor layers and the first and second planar semiconductor layers are made of silicon.