SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR

• US 20110303985A1
• Filed: 05/23/2011
• Published: 12/15/2011
• Est. Priority Date: 06/09/2010
• Status: Active Grant

• Current Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Original Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Inventors: Masuoka, Fujio, Nakamura, Hiroki, Arai, Shintaro, Kudo, Tomohiko, Jiang, Yu, Chui, King-Jien, Li, Yisuo, Li, Xiang, Chen, Zhixian, Shen, Nansheng, Bliznetsov, Vladimir, Buddharaju, Kavitha Devi, Singh, Navab
• Granted Patent: US 8,486,785 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.

Claims

1. A semiconductor device comprising:

a first planar semiconductor layer;

a first columnar semiconductor layer formed on the first planar semiconductor layer;

a first highly doped semiconductor layer formed in a lower region of the first columnar semiconductor layer and the first planar semiconductor layer;

a second highly doped semiconductor layer formed in an upper region of the first columnar semiconductor layer and having a conductivity type same as a conductivity type of the first highly doped semiconductor layer;

a first gate insulating film formed so as to surround the first columnar semiconductor layer on a sidewall of the first columnar semiconductor layer between the first highly doped semiconductor layer and the second highly doped semiconductor layer;

a first gate electrode formed so as to surround the first gate insulating film on the first gate insulating film;

a first insulating film formed between the first gate electrode and the first planar semiconductor layer;

a first insulating film sidewall formed so as to contact a top surface of the first gate electrode and an upper sidewall of the first columnar semiconductor layer, and to surround the upper region of the first columnar semiconductor layer;

a second metal-semiconductor compound layer formed in the same layer as the first planar semiconductor layer so as to contact the first highly doped semiconductor layer; and

a first electric contact formed on the second highly doped semiconductor layer, wherein

the first electric contact and the second highly doped semiconductor layer are connected directly and

the first gate electrode includes a first metal-semiconductor compound layer.

2. The semiconductor device according to claim 1 further comprising a fifth metal-semiconductor compound layer formed between the first electric contact and the second highly doped semiconductor layer, wherein:

the metal of the fifth metal-semiconductor compound is various types of metal which are different from the metal of the first metal-semiconductor compound layer and the metal of the second metal-semiconductor compound layer.

3. The semiconductor device according to claim 1, wherein the first gate electrode further comprising a first metal film formed between the first gate insulating film and the first metal-semiconductor compound layer.

8. A fabrication method for a semiconductor device, the fabrication method is a method for fabricating the semiconductor device according to claim 3, the fabrication method of aforesaid semiconductor device comprising the steps of:

preparing a structure including;

the first planar semiconductor layer;

the first columnar semiconductor layer formed on the first planar semiconductor layer, a hard mask being formed in a top surface of the first columnar semiconductor layer;

the first highly doped semiconductor layer formed in a lower region of the first planar semiconductor layer and the first columnar semiconductor layer; and

a third insulating film formed on the hard mask and the first planar semiconductor layer;

forming a fourth insulating film, a third metal film, and a first semiconductor layer sequentially on the structure;

etching the first semiconductor layer to remain the first semiconductor layer in a shape of a sidewall on a sidewall of the first columnar semiconductor layer;

etching the third metal film to remain the sidewall of the first columnar semiconductor layer in a shape of the sidewall;

etching the fourth insulating film to remain the sidewall of the first columnar semiconductor layer in a shape of the sidewall;

forming a second semiconductor layer on results of the step of etching the fourth insulating film;

forming a third semiconductor layer so that results of the step of forming the second semiconductor layer are embedded,

planarizing the second semiconductor layer, the third semiconductor layer and the first semiconductor layer and etching back so that an upper region of the third metal film is exposed;

etching the third metal film made remaining in the shape of the sidewall and the fourth insulating film made remaining in the shape of the sidewall so as to expose an upper sidewall of the first columnar semiconductor layer, and then forming the first metal film and the first gate insulating film;

forming a second highly doped semiconductor layer having a conductivity type same as the first highly doped semiconductor layer in the upper region of the first columnar semiconductor layer;

forming an oxide film and a nitride film sequentially on results of the step of forming the second highly doped semiconductor layer;

etching the oxide film and the nitride film so that the oxide film and the nitride film remain in a shape of the sidewall on the upper sidewall of the first columnar semiconductor layer and the sidewall of the hard mask, and then forming the first insulating film sidewall;

etching the first semiconductor layer, the second semiconductor layer and the third semiconductor layer to remain at least a part of the first semiconductor layer and the second semiconductor layer so as to surround the first metal film on the first metal film sidewall;

etching to remove the third insulating film exposed in the step of etching the semiconductor layer and exposing the first planar semiconductor layer;

by depositing and then annealing a metal on results of the step of exposing the first planar semiconductor layer, making react the deposited metal with a semiconductor included in the first planar semiconductor layer, and making react the deposited metal with a semiconductor included in the first semiconductor layer and the second semiconductor layer made to remain on the first metal film; and

by removing an unreacted metal in the step of making react the metal and the semiconductor, forming the second metal-semiconductor compound layer in the first planar semiconductor layer, and forming the first metal-semiconductor compound layer in the first gate electrode.

9. The fabrication method of the semiconductor device according to claim 8 further comprising the step of:

directly forming the first electric contact on the second highly doped semiconductor layer formed in the upper part of the first columnar semiconductor layer.

10. The semiconductor device according to claim 2, wherein the first gate electrode further comprising a first metal film formed between the first gate insulating film and the first metal-semiconductor compound layer.

4. A semiconductor device comprising a first transistor and a second transistor, the first transistor comprising:

a first planar semiconductor layer;

a first columnar semiconductor layer formed on the first planar semiconductor layer;

a first highly doped semiconductor layer of a second-conductivity type formed in the lower region of the first columnar semiconductor layer and the first planar semiconductor layer;

a second highly doped semiconductor layer of the second-conductivity type formed in the upper region of the 1st columnar semiconductor layer;

a first gate insulating film formed so as to surround the first columnar semiconductor layer on a sidewall of the first columnar semiconductor layer between the first highly doped semiconductor layer and the second highly doped semiconductor layer;

a first gate electrode formed so as to surround the first gate insulating film on the first gate insulating film;

a first insulating film formed between the first gate electrode and the first planar semiconductor layer;

a first insulating film sidewall formed so as to contact to a top surface of the first gate electrode and an upper sidewall of the first columnar semiconductor layer and to surround the upper region of the first columnar semiconductor layer;

a second metal-semiconductor compound layer formed in the same layer as the first planar semiconductor layer so as to contact to the first highly doped semiconductor layer; and

a first electric contact formed on the second highly doped semiconductor layer, and

the second transistor comprising;

a second planar semiconductor layer;

a second columnar semiconductor layer formed on the second planar semiconductor layer;

a third highly doped semiconductor layer of a first conductivity type formed in a lower region of the second columnar semiconductor layer and the second planar semiconductor layer;

a fourth highly doped semiconductor layer of the first conductivity type formed in an upper region of the second columnar semiconductor layer;

a second gate insulating film formed so as to surround the second columnar semiconductor layer on a sidewall of the second columnar semiconductor layer between the third highly doped semiconductor layer and the fourth highly doped semiconductor layer;

a second gate electrode formed so as to surround the second gate insulating film on the second gate insulating film;

a second insulating film formed between the second gate electrode and the second planar semiconductor layer;

a second insulating film sidewall formed so as to contact to a top surface of the second gate electrode and an upper sidewall of the second columnar semiconductor layer, and to surround the upper region of the second columnar semiconductor layer;

a fourth metal-semiconductor compound layer formed in the same layer as the second planar semiconductor layer so as to contact the third highly doped semiconductor layer; and

a second electric contact formed on the fourth highly doped semiconductor layer, wherein

the first electric contact and the second highly doped semiconductor layer are connected directly,

the second electric contact and the fourth highly doped semiconductor layer are connected directly,

the first gate electrode includes a first metal-semiconductor compound layer, and

the second gate electrode includes a third metal-semiconductor compound layer.

5. The semiconductor device according to claim 4 further comprising:

a fifth metal-semiconductor compound layer formed between the first electric contact and the second highly doped semiconductor layer;

a sixth metal-semiconductor compound layer formed between the second electric contact and the fourth highly doped semiconductor layer, wherein

the metal of the fifth metal-semiconductor compound is various types of metal that are different from the metal of the first metal-semiconductor compound and the metal of the second metal-semiconductor compound, and

the metal of the sixth metal-semiconductor compound is various types of metal that are different from the metal of the third metal-semiconductor compound and the metal of the fourth metal-semiconductor compound.

6. The semiconductor device according to claim 4 further comprising:

a first metal film formed between the first gate insulating film and the first metal-semiconductor compound layer; and

a second metal film formed between the second gate insulating film and the third metal-semiconductor compound layer.

7. The semiconductor device according to claim 6, wherein:

the first gate insulating film and the first metal film are formed from materials for configuring the first transistor to be an enhancement type, and

the second gate insulating film and the second metal film are formed from materials for configuring the second transistor to be an enhancement type.

11. The semiconductor device according to claim 5 further comprising:

a first metal film formed between the first gate insulating film and the first metal-semiconductor compound layer; and

a second metal film formed between the second gate insulating film and the third metal-semiconductor compound layer.

12. The semiconductor device according to claim 11, wherein:

the first gate insulating film and the first metal film are formed from materials for configuring the first transistor to be an enhancement type, and

the second gate insulating film and the second metal film are formed from materials for configuring the second transistor to be an enhancement type.