METHODS OF AND ARRANGEMENTS FOR OFFSET COMPENSATION OF AN ANALOG-TO-DIGITAL CONVERTER

• US 20110304489A1
• Filed: 06/15/2010
• Published: 12/15/2011
• Est. Priority Date: 06/15/2010
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: Zoran Corporation (Qualcomm, Inc.)
• Inventors: SUNDBLAD, Rolf, Christer, Jansson
• Granted Patent: US 8,212,697 B2
• Time in Patent Office: Days
• US Class Current: 341/118
• CPC Class Codes: H03M 1/1019 by storing a corrected or correction value in a digital look-up table
• CPC Class Codes: H03M 1/1215 using time-division multiplexing

Abstract

An arrangement is disclosed for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain. The arrangement comprises the time-interleaved analog-to-digital converter, an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels, a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels, and offset compensation means. The offset compensation means are adapted to perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain, and to perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.

Claims

1. A method of offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain, comprising:

estimating a mean offset for the plurality of computing channels;

estimating a residual computing channel specific offset for each of the plurality of computing channels;

performing offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain; and

performing offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.

2. The method of claim 1, further comprising scaling the signal range based on a scaling value dependent of a maximum offset compensation before performing offset compensation in the digital domain.

3. The method of claim 1, further comprising scaling the signal range based on a scaling value dependent of a reference signal level before performing offset compensation in the analog domain.

4. The method of claim 1, further comprising shifting the signal range based on a shift value dependent of a reference signal level before performing offset compensation in the analog domain.

5. The method of claim 1, further comprising limiting the signal range after performing offset compensation in the digital domain.

6. The method of claim 5, wherein the signal range is limited symmetrically around a mid code.

7. The method of claim 5, wherein the limited signal range is shifted such that the shifted, limited signal range starts at a starting value.

8. The method of claim 7, wherein the starting value is a fixed, non-negative value.

9. The method of claim 1, wherein the step of estimating the mean offset for the plurality of computing channels is performed in association with a process of producing the time-interleaved analog-to-digital converter.

10. The method of claim 1, wherein the step of estimating the mean and residual offsets for the plurality of computing channels comprises:

for each of the plurality of computing channels;

analog-to-digital converting a reference signal; and

comparing a calibration value with the analog-to-digital converted reference signal; and

estimating the mean and residual offsets based on a result of the comparisons.

11. The method of claim 10, further comprising turning off a current clamping during the steps of analog-to-digital converting a reference signal and comparing a calibration value with the analog-to-digital converted reference signal.

12. The method of claim 1, further comprising:

estimating, in association with a process of producing the time-interleaved analog-to-digital converter, a gain compensation value for each of a plurality of gain settings of the time-interleaved analog-to-digital converter; and

performing gain compensation of the time-interleaved analog-to-digital converter based on the estimated gain compensation values and a current gain setting.

13. An arrangement for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain, comprising:

the time-interleaved analog-to-digital converter;

an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels;

a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels; and

offset compensation means adapted to;

perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain; and

perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.

14. The arrangement of claim 13, wherein the analog offset estimation and compensation unit comprises:

an offset integration unit adapted to determine the mean offset by integration;

a settling check unit adapted to determine whether the mean offset has converged; and

a loop gain correction unit adapted to determine one or more integration parameters associated with the offset integration unit.

15. The arrangement of claim 13, further comprising an update timing controller adapted to determine an update time for the mean offset value.

16. The arrangement of claim 13, further comprising an amplifier preceding the time-interleaved analog-to-digital converter, and wherein the offset compensation means comprises an offset digital-to-analog converter having an input connected to an output of the analog offset estimation and compensation unit and an output connected to an input of the amplifier for performing offset compensation in the analog domain.

17. The arrangement of claim 13, further comprising:

a first memory having stored thereon a gain compensation value, estimated in association with a process of producing the time-interleaved analog-to-digital converter, for each of a plurality of gain settings of the amplifier; and

gain compensation means adapted to perform gain compensation of the time-interleaved analog-to-digital converter based on the estimated gain compensation values and a current gain setting.

18. The arrangement of claim 13, wherein the offset compensation means comprises an adder having an input connected to an output of the digital offset estimation and compensation unit and another input associated with an output of the time-interleaved analog-to-digital converter for performing offset compensation in the digital domain.

19. The arrangement of claim 13, further comprising a range scaler associated with an output of the time-interleaved analog-to-digital converter, with an input of the analog offset estimation and compensation unit and with an input of the digital offset estimation and compensation unit, and adapted to scale the signal range based on a scaling value dependent of a maximum offset compensation in the digital domain.

20. The arrangement of claim 13, further comprising a range scaler associated with an input of the time-interleaved analog-to-digital converter, and adapted to scale the signal range based on a scaling value dependent of a reference signal level at the input of the time-interleaved analog-to-digital converter.

21. The arrangement of claim 13, further comprising a range shifter associated with an input of the time-interleaved analog-to-digital converter, and adapted to shift the signal range based on a shift value dependent of a reference signal level at the input of the time-interleaved analog-to-digital converter.

22. The arrangement of claim 13, further comprising a signal range limiter associated with an output of the digital offset estimation and compensation unit.

23. The arrangement of claim 22, wherein the limiter is adapted to limit the signal range symmetrically around a mid code.

24. The arrangement of claim 22, further comprising circuitry adapted to shift the limited signal range such that the shifted, limited signal range starts at a starting value.

25. The arrangement of claim 24, wherein the starting value is a fixed, non-negative value.

26. The arrangement of claim 13,

further comprising a comparing unit adapted to compare a calibration value with an analog-to-digital converted reference signal;

wherein the analog offset estimation and compensation unit is adapted to estimate the mean offset based on an output of the comparing unit; and

wherein the digital offset estimation and compensation unit is adapted to estimate the residual computing channel specific offset based on an output of the comparing unit.

27. The arrangement of claim 26, further comprising:

a current clamping; and

a current clamping controller adapted to turn off the current clamping during the comparison by the comparing unit of the calibration value with the analog-to-digital converted reference signal.

28. The arrangement of claim 13,

further comprising a bypass switch for bypassing the analog offset estimation and compensation unit;

and

wherein the digital offset estimation and compensation unit is adapted, when the bypass switch is in a state to bypass the analog offset estimation and compensation unit, either to;

estimate a total computing channel specific offset for each of the plurality of computing channels; and

perform offset compensation in the digital domain of each of the plurality of channels based on respective total computing channel specific offset;

or to

estimate a residual computing channel specific offset for each of the plurality of computing channels; and

perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.

29. The arrangement of claim 13, further comprising:

a second memory having stored thereon offset values, estimated in association with a process of producing the time-interleaved analog-to-digital converter; and

a first stored values switch for feeding the analog offset estimation and compensation unit with the stored offset values, the analog offset estimation and compensation unit being adapted to, when the first stored values switch is in a state to feed the analog offset estimation and compensation unit with the stored offset values, perform offset compensation of the time-interleaved analog-to-digital converter in the analog domain based on the stored offset values; and

/or

a second stored values switch for feeding the digital offset estimation and compensation unit with the stored offset values, the digital offset estimation and compensation unit being adapted to, when the second stored values switch is in a state to feed the digital offset estimation and compensation unit with the stored offset values, perform offset compensation of the time-interleaved analog-to-digital converter in the digital domain based on the stored offset values.

30. The arrangement of claim 13,

further comprising an all analog offset compensation switch to bypass the digital offset estimation and compensation unit;

and

wherein the analog offset estimation and compensation unit is adapted to, when the all analog offset compensation switch is in a state to bypass the digital offset estimation and compensation unit;

estimate a total computing channel specific offset for each of the plurality of computing channels; and

perform offset compensation in the analog domain of each of the plurality of channels based on respective total computing channel specific offset.

31. An application specific integrated circuit comprising one or more arrangements according to claim 13.

32. An electronic device comprising the one or more arrangements according to claim 13.

33. The electronic device of claim 32, wherein the electronic device is a video analog front-end, a radio receiver, a television set, a liquid-crystal display, a computer monitor, a digital camera, a projector, a computer, a laptop, or a portable electronic device.