Semiconductor Memory Having Volatile and Multi-Bit, Non-Volatile Functionality and Methods of Operating
First Claim
1. A semiconductor memory cell comprising:
- a substrate having a first conductivity type;
a first region embedded in the substrate at a first location of the substrate and having a second conductivity type;
a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory;
a buried insulator layer bounding a bottom of said floating body;
a trapping layer positioned in between the first and second locations and above a surface of the substrate;
the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and
a control gate positioned above the trapping layer.
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Accused Products
Abstract
A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, and a control gate positioned above the trapping layer.
191 Citations
32 Claims
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1. A semiconductor memory cell comprising:
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a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a buried insulator layer bounding a bottom of said floating body; a trapping layer positioned in between the first and second locations and above a surface of the substrate;
the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; anda control gate positioned above the trapping layer. - View Dependent Claims (3, 6, 7, 9, 10, 11)
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2. (canceled)
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4-5. -5. (canceled)
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8. (canceled)
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12-21. -21. (canceled)
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22. A semiconductor memory cell comprising:
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a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a buried insulator layer bounding a bottom of said floating body; a trapping layer positioned in between the first and second locations and above a surface of the substrate;
the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; anda control gate positioned above the trapping layer; wherein said cell is configured so that one of said first and second storage locations interacts with said floating body so that said memory cell provides both volatile and non-volatile memory functionality, and the other of said first and second storage locations is configured to store non-volatile data that is not used as volatile memory by said floating body. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A memory array comprising a plurality of rows and columns of semiconductor memory cells, a plurality of said cells each comprising:
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a floating body region to store volatile memory; first and second regions; a trapping layer positioned in between the first and second locations and above a surface of the substrate;
the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another;a control gate positioned above the trapping layer; and control terminals defining the columns of said memory array are electrically connected to said first and second regions. - View Dependent Claims (29, 30, 31, 32)
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Specification