PHASE AND FREQUENCY RE-LOCK IN SYNCHRONOUS ETHERNET DEVICES

• US 20110305173A1
• Filed: 06/08/2011
• Published: 12/15/2011
• Est. Priority Date: 06/10/2010
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wang, Peiqing, Lin, Xiaotong, Tazebay, Mehmet, Wang, Linghsiao
• Granted Patent: US 8,565,270 B2
• Time in Patent Office: Days
• US Class Current: 370/296
• CPC Class Codes: H04J 3/0641 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04J 3/0644 External master-clock
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge

Abstract

A first PHY may be coupled to a second PHY via a network link. The first PHY may transition from a role of timing master for the network link to a role of timing slave for the network link. During a first time interval subsequent to the transition, the PHYs may communicate half-duplex over the link while the first PHY synchronizes to a transmit clock of the second PHY. During a second time interval, the PHYs may communicate full-duplex while the second Ethernet PHY synchronizes to a transmit clock of the first PHY. Also during the second time interval, the first PHY may determine that the first PHY and the second PHY are synchronized. Subsequent to the determination, the PHYs may begin full-duplex communication of data on the network link.

Claims

1. A method comprising:

in a first Ethernet PHY that is coupled to a second Ethernet PHY via a network link;

transitioning from a role of timing master for said network link to a role of timing slave for said network link;

during a first time interval after said transitioning, synchronizing one or more circuits of said first Ethernet PHY to a transmit clock of said second Ethernet PHY, wherein communications on said network link are half-duplex during said first time interval; and

during a second time interval after said first time interval, determining that said first Ethernet PHY and said second Ethernet PHY have achieved synchronization, wherein communications on said network link are full-duplex during said second time interval.

2. The method according to claim 1, wherein, during said first time interval, said first Ethernet PHY transmits only zeros onto said network link while receiving IDLE signals via said network link.

3. The method according to claim 1, wherein a role of said first Ethernet PHY as either 802.3 master or 802.3 slave is the same before, during, and after said transitioning.

4. The method according to claim 1, wherein:

after said second time interval, said first Ethernet PHY begins communicating data on said link; and

from a time instant at which said transitioning is initiated through said beginning of said data communication on said network link, said first Ethernet PHY and said second Ethernet PHY do not enter an autonegotiation mode.

5. The method according to claim 1, wherein said transitioning is initiated in response to a determination to change the primary reference clock to which said first Ethernet PHY and said second Ethernet PHY are to be synchronized.

6. A method comprising:

in a first Ethernet PHY that is coupled to a second Ethernet PHY via a network link;

transitioning from a role of timing slave for said network link to a role of timing master for said network link;

during a first time interval after said transitioning, communicating half-duplex over said network link,

during a second time interval after said first time interval, synchronizing one or more circuits of first Ethernet PHY to a transmit clock of said second Ethernet PHY, and

during said second time interval, determining that said first Ethernet PHY and said second Ethernet PHY have achieved synchronization, wherein communications on said network link are full-duplex during said second time interval.

7. The method according to claim 6, wherein, during said first time interval, said first Ethernet PHY transmits only zeros onto said network link while receiving IDLE signals via said network link.

8. The method according to claim 6, wherein a role of said first Ethernet PHY as either 802.3 master or 802.3 slave is the same before, during, and after said transitioning.

9. The method according to claim 6, wherein:

subsequent to said second time interval, said first Ethernet PHY begins communicating data on said link; and

from a time instant at which said transitioning is initiated through said beginning of said data communication on said network link, said first Ethernet PHY and said second Ethernet PHY do not enter an autonegotiation mode.

10. The method according to claim 6, wherein said transitioning is initiated in response to a determination to change the primary reference clock to which said first Ethernet PHY and said second Ethernet PHY are to be synchronized.

11. A system comprising:

a first Ethernet PHY, said first Ethernet PHY being coupled to a second Ethernet PHY via a network link, and said first Ethernet PHY being operable to;

transition from a role of timing master for said network link to a role of timing slave for said network link;

during a first time interval after said transitioning, synchronizing one or more circuits of said first Ethernet PHY to a transmit clock of said second Ethernet PHY, wherein communications on said network link are half-duplex during said first time interval;

during a second time interval after said first time interval, determine that said first Ethernet PHY and said second Ethernet PHY have achieved synchronization, wherein communications on said network link are full-duplex during said second time interval.

12. The system according to claim 11, wherein, during said first time interval, said first Ethernet PHY transmits only zeros onto said network link while receiving IDLE signals via said network link.

13. The system according to claim 11, wherein a role of said first Ethernet PHY as either 802.3 master or 802.3 slave is the same before, during, and after said transitioning.

14. The system according to claim 11, wherein:

after said second time interval, said first Ethernet PHY begins communicating data on said link; and

from a time instant at which said transition is initiated through said beginning of said data communication on said network link, said first Ethernet PHY and said second Ethernet PHY do not enter an autonegotiation mode.

15. The system according to claim 11, wherein said transition is initiated in response to a determination to change the primary reference clock to which said first Ethernet PHY and said second Ethernet PHY are to be synchronized.

16. A system comprising:

a first Ethernet PHY, said first Ethernet PHY being coupled to a second Ethernet PHY via a network link, and said first Ethernet PHY being operable to;

transition from a role of timing slave for said network link to a role of timing master for said network link;

during a first time interval after said transitioning, communicating half-duplex over said network link,

during a second time interval after said first time interval, synchronize one or more circuits of said first Ethernet PHY to a transmit clock of said second Ethernet PHY; and

during said second time interval, determine that said first Ethernet PHY and said second Ethernet PHY have achieved synchronization, wherein communications on said network link are full-duplex during said second time interval.

17. The system according to claim 16, wherein, during said first time interval, said first Ethernet PHY transmits only zeros onto said network link while receiving IDLE signals via said network link.

18. The system according to claim 16, wherein a role of said first Ethernet PHY as either 802.3 master or 802.3 slave is the same before, during, and after said transitioning.

19. The system according to claim 16, wherein:

subsequent to said second time interval, said first Ethernet PHY begins communicating data on said link; and

from a time instant at which said transitioning is initiated through said beginning of said data communication on said network link, said first Ethernet PHY and said second Ethernet PHY do not enter an autonegotiation mode.

20. The system according to claim 16, wherein said transition is initiated in response to a determination to change the primary reference clock to which said first Ethernet PHY and said second Ethernet PHY are to be synchronized.