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High-Speed Signaling Systems With Adaptable Pre-Emphasis and Equalization

  • US 20110305271A1
  • Filed: 08/23/2011
  • Published: 12/15/2011
  • Est. Priority Date: 01/20/2005
  • Status: Active Grant
First Claim
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1. A first integrated circuit, comprising:

  • a linear equalizer to receive a digital bit stream from a second integrated circuit over a signal path and to equalize the digital bit stream and generate an output; and

    a decision feedback equalizer having a tap, the tap driven based on a historical data value conveyed by the digital bit stream, the decision feedback equalizer to equalize the output;

    where the first integrated circuit has two equalization modes, including a first mode where the tap is used to equalize data received from the second integrated circuit, and a second mode where the tap is disabled and is not used to equalize data received from the second integrated circuit.

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