Image Processing Address Generator

• US 20110307684A1
• Filed: 06/10/2010
• Published: 12/15/2011
• Est. Priority Date: 06/10/2010
• Status: Active Grant

• Current Assignee: MobilEye Vision Technologies Ltd. (Intel Corporation)
• Original Assignee: MobilEye Vision Technologies Ltd. (Intel Corporation)
• Inventors: Sixsou, Emmanuel, Navon, Mois, Kreinin, Yosef, Dogon, Gil, Arbeli, Yosi, Sajman, Roman
• Granted Patent: US 8,892,853 B2
• Time in Patent Office: Days
• US Class Current: 712/3
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3555 using scaling, e.g. multiplication of index
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06V 10/955 using specific electronic processors
• CPC Class Codes: G06V 20/56 exterior to a vehicle by using sensors mounted on the vehicle

Abstract

An image processing system including a vector processor and a memory adapted for attaching to the vector processor. The memory is adapted to store multiple image frames. The vector processor includes an address generator operatively attached to the memory to access the memory. The address generator is adapted for calculating addresses of the memory over the multiple image frames. The addresses may be calculated over the image frames based upon an image parameter. The image parameter may specify which of the image frames are processed simultaneously. A scalar processor may be attached to the vector processor. The scalar processor provides the image parameter(s) to the address generator for address calculation over the multiple image frames. An input register may be attached to the vector processor. The input register may be adapted to receive a very long instruction word (VLIW) instruction. The VLIW instruction may be configured to transfer only: (i) parameters for image processing calculations over the image frames by the ALU units and (ii) a single bit to the address generator.

Claims

1. An image processing system comprising:

a vector processor; and

a memory adapted for operatively attaching to said vector processor, wherein said memory is adapted to store a plurality of image frames,

wherein said vector processor includes an address generator operatively attached to said memory to access said memory, and

wherein said address generator is adapted for calculating addresses of said memory over said image frames.

2. The image processing system according to claim 1, wherein said addresses are calculated over said image frames based upon an image parameter.

3. The image processing system according to claim 2, wherein said image parameter specifies which of the image frames are processed simultaneously.

4. The image processing system according to claim 3, further comprising a scalar processor operatively attached to said vector processor, wherein said scalar processor provides said image parameter to said address generator for said calculating over said image frames.

5. The image processing system according to claim 1, further comprising an input register operatively attached to said vector processor, wherein said input register is adapted to receive a very long instruction word (VLIW) instruction wherein only one bit of said VLIW instruction is provided to said address generator.

6. The image processing system according to claim 1, wherein said vector processor includes:

at least one arithmetic and logic unit (ALU); and

an input register adapted for receiving a very long instruction word (VLIW) instruction, wherein said VLIW instruction is configured to transfer only;

(i) operation codes for image processing calculations over said image frames by said at least one ALU unit and (ii) a single bit to said address generator.

7. The image processing system according to claim 1, wherein said addresses are calculated over said multiple image frames based upon at most one image size parameter which specifies a dimension of said image frames.

8. The image processing system according to claim 1, wherein said addresses are calculated over said multiple image frames based upon at most two image size parameters which specify a dimension of said image frames.

9. A method of processing images in a system including a vector processor and a memory, wherein the vector processor includes an address generator operatively attached to the memory to access the memory, wherein said address generator is adapted for calculating addresses of said memory, the method comprising:

storing a plurality of image frames in the memory;

accessing the memory by the address generator;

loading an image parameter;

calculating addresses for said image frames based upon said image parameter; and

processing in parallel image data stored in said image frames.

10. The method according to claim 9, wherein said loading is performed in a register operatively attached to the address generator.

11. The method according to claim 9, further comprising receiving a VLIW instruction for said processing in parallel.

12. The method according to claim 11, wherein said processing in parallel is performed by the vector processor according to said VLIW instruction, wherein said loading of said image parameter is performed externally to said VLIW instruction

13. The method according to claim 12, further comprising receiving by said address generator only a single bit of said VLIW instruction to enable said calculating addresses.

14. The method according to claim 9, wherein said image parameter specifies at least two of said image frames to be processed in parallel.

15. The method according to claim 9, wherein said calculating is based upon said image parameter including at most two image size parameters which specify the size of said image frames.

16. The method according to claim 9, wherein said calculating is based upon said image parameter including at most one image size parameter which specifies the size of said image frames.

17. A method of processing images in a system including a vector processor and a memory, wherein the vector processor includes an address generator operatively attached to the memory to access the memory, wherein said address generator is adapted for calculating addresses of said memory, the method comprising:

storing an image frame in the memory;

loading and reading a window parameter which specifies multiple windows within said image frame;

calculating addresses for said multiple windows within said image frame based upon said image parameter; and

processing in parallel image data of said multiple windows stored at said addresses.

18. The method according to claim 17, further comprising receiving a VLIW instruction for said processing in parallel.

19. The method according to claim 18, wherein said processing in parallel is performed by the vector processor according to said VLIW instruction, wherein said loading said window parameter is performed externally to said VLIW instruction.

20. The method according to claim 17, further comprising receiving by said address generator only a single bit of said VLIW instruction to enable said calculating.