SEMICONDUCTOR CHIP WITH FINE PITCH LEADS FOR NORMAL TESTING OF SAME

• US 20110309358A1
• Filed: 12/27/2010
• Published: 12/22/2011
• Est. Priority Date: 06/17/2010
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: SUH, Min Suk, HAN, Kwon Whan, YANG, Seung Taek, KIM, Jong Hoon
• Application Number:
  US12/979,317
• Publication Number:
  US 20110309358A1
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices

Abstract

A semiconductor chip includes a semiconductor substrate having a top surface and a bottom surface. A circuit layer having bonding pads may be formed over the top surface of the semiconductor substrate. Through electrodes may be formed to pass from a bottom surface to a top surface of the semiconductor substrate, and the through electrodes may comprise through parts connected with the bonding pads and projecting parts formed over the bottom surface of the semiconductor substrate and electrically connected with the through parts. Test pad parts may be disposed over the bottom surface of the semiconductor substrate and is connected with the through electrodes to test normal operation of the circuit layer and electrical connections of the through electrodes and the circuit layer.

Claims

1. A semiconductor chip comprising:

a semiconductor substrate having a top surface and a bottom surface;

a circuit layer formed over the top surface of the semiconductor substrate and having bonding pads;

through electrodes formed to pass from a bottom surface to the top surface of the semiconductor substrate, and comprising through parts connected with the bonding pads and projecting parts formed on the bottom surface of the semiconductor substrate; and

test pad parts disposed on the bottom surface of the semiconductor substrate and connected with the through electrodes.

2. The semiconductor chip according to claim 1, wherein is the test pad parts comprise:

test pads formed over the bottom surface of the semiconductor substrate at positions near the through electrodes; and

test redistribution lines connecting the through electrodes and the test pads with each other.

3. The semiconductor chip according to claim 2, wherein the test redistribution lines are electrically connected with the projecting parts of the through electrodes, and the projecting parts are formed over the through parts of the through electrodes.

4. The semiconductor chip according to claim 2, wherein the projecting part of each through electrode has a first size when viewed from the top, and each test pad has a second size greater than the first size.

5. The semiconductor chip according to claim 2, wherein each test pad has the shape of any one selected among a circle, an oval, and polygons when viewed from the top.

6. The semiconductor chip according to claim 2, further comprising:

a lower insulation pattern having first openings that expose the projecting parts of the through electrodes and the test pads of the test pad parts, and covering a portion of the bottom surface of the semiconductor substrate.

7. The semiconductor chip according to claim 6, wherein the lower insulation pattern has second openings that expose portions of test redistribution lines of the test pad parts.

8. The semiconductor chip according to claim 1, wherein the through electrodes comprise redistribution lines that electrically connect the through parts and the projecting parts with each other.

9. The semiconductor chip according to claim 8, wherein the test pad parts comprise:

test pads formed over the bottom surface of the semiconductor substrate at positions near the through electrodes; and

test redistribution lines connecting the redistribution lines of the through electrodes and the test pads with each other.

10. The semiconductor chip according to claim 9, wherein, when viewed from the top, the projecting part of each through electrode has a first size and each test pad has a second size greater than the first size.

11. The semiconductor chip according to claim 9, wherein each test pad has the shape of any one selected among a circle, an oval, and polygons when viewed from the top.

12. The semiconductor chip according to claim 9, further comprising:

a lower insulation pattern having first openings that expose the projecting parts of the through electrodes and the test pads of the test pad parts, and cover portions of the bottom surface of the semiconductor substrate.

13. The semiconductor chip according to claim 12, wherein the lower insulation pattern has second openings that expose portions of test redistribution lines of the test pad parts.

14. The semiconductor chip according to claim 1, further comprising:

upper connection members formed over the bonding pads; and

lower connection members formed over the projecting parts of the through electrodes.

15. The semiconductor chip according to claim 14, wherein each of the upper and lower connection members comprises a conductive member that includes any one of a solder, a metal, an ACF (anisotropic conductive film) and an ACP (anisotropic conductive paste).

16. The semiconductor chip according to claim 1, further comprising:

ground pads formed over the top surface of the semiconductor substrate; and

ground through electrodes formed to pass from the bottom surface to the top surface of the semiconductor substrate, and electrically connected with the ground pads.

17. The semiconductor chip according to claim 16, further comprising:

additional elements formed over the bottom surface of the semiconductor substrate and electrically connected with the ground through electrodes and the through electrodes.

18. The semiconductor chip according to claim 17, wherein each of the additional elements comprises a passive element or an active element.

19. The semiconductor chip according to claim 17, wherein each of the additional elements comprises:

a first metal line formed over the bottom surface of the semiconductor substrate to be connected with the ground through electrode;

a second metal line formed to be placed over the first metal line in such a way as to partially overlap with the first metal line and be connected with the through electrode; and

an insulation member interposed between the first and second metal lines.

20. The semiconductor chip according to claim 19, wherein each of the additional elements comprises a resistor or a capacitor.