Flat panel display apparatus and method of manufacturing the same

• US 20110309362A1
• Filed: 04/06/2011
• Published: 12/22/2011
• Est. Priority Date: 06/17/2010
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Yoon, Joo-Sun, Wang, Seong-Min
• Granted Patent: US 8,749,725 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

A flat panel display apparatus including a gate electrode on a substrate, a first insulating layer and a semiconductor layer sequentially stacked on the gate electrode and including a transparent conductive oxide, a capacitor first electrode extending on a plane on which the gate electrode extends, and a capacitor second electrode extending on a plane on which the semiconductor layer extends and including a material of the semiconductor layer, wherein the first insulating layer is between the capacitor second electrode and the semiconductor layer, source and drain electrodes that are separated by a second insulating layer and are connected to the semiconductor layer and the capacitor second electrode, a third insulating layer covering the source and drain electrodes, and a pixel electrode electrically connected to the source or drain electrode on the third insulating layer and being electrically connected to one of the source electrode and/or the drain electrode.

Claims

1. A flat panel display apparatus, comprising:

a gate electrode disposed on a substrate;

a first insulating layer disposed on the gate electrode;

a semiconductor layer disposed on the first insulating layer and including a transparent conductive oxide;

a capacitor first electrode extending on a same plane as that on which the gate electrode extends, and a capacitor second electrode extending on a same plane as that on which the semiconductor layer extends and including a same material as the semiconductor layer, wherein the first insulating layer is interposed between the capacitor second electrode and the semiconductor layer;

source and drain electrodes that are separated by a second insulating layer and are connected to the semiconductor layer and the capacitor second electrode;

a third insulating layer covering the source electrode and the drain electrode; and

a pixel electrode disposed on the third insulating layer and electrically connected to one of the source electrode and the drain electrode.

2. The flat panel display apparatus as claimed in claim 1, wherein the gate electrode includes a transparent conductive layer, and a metallic layer disposed on the transparent conductive layer.

3. The flat panel display apparatus as claimed in claim 2, wherein the capacitor first electrode includes a same material as the transparent conductive layer of the gate electrode.

4. The flat panel display apparatus as claimed in claim 2, wherein outer etched surfaces of the transparent conductive layer and the metallic layer are disposed on a same plane.

5. The flat panel display apparatus as claimed in claim 1, wherein the capacitor first electrode includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), and/or aluminium zinc oxide (AZO).

6. The flat panel display apparatus as claimed in claim 1, wherein the transparent conductive oxide includes oxygen (O) and at least one of gallium (Ga), Indium (In), zinc (Zn), and/or tin (Sn).

7. The flat panel display apparatus as claimed in claim 1, wherein the first insulating layer has a higher permittivity than the third insulating layer.

8. The flat panel display apparatus as claimed in claim 1, wherein the first insulating layer includes an inorganic insulating material and the third insulating layer includes an organic insulating material.

9. The flat panel display apparatus as claimed in claim 1, further comprising a data interconnection line disposed on the same plane on which the source electrode and drain electrode are disposed and via which a data voltage to the source electrode and the drain electrode is applied.

10. The flat panel display apparatus as claimed in claim 1, wherein the third insulating layer is thicker than the first insulating layer.

11. The flat panel display apparatus as claimed in claim 1, wherein a portion of the second insulating layer on the capacitor second electrode is removed and the capacitor second electrode directly contacts the third insulating layer.

12. The flat panel display apparatus as claimed in claim 11, further comprising a capacitor third electrode that is disposed on a portion of the capacitor second electrode corresponding to the removed portion of the second insulating layer, and includes a same material as the source electrode and the drain electrode.

13. The flat panel display apparatus as claimed in claim 12, wherein the first insulating layer and the second insulating layer include a same insulating material.

14. The flat panel display apparatus as claimed in claim 13, wherein the first insulating layer and the second insulating layer include silicon oxide (SiOx).

15. The flat panel display apparatus as claimed in claim 1, wherein the pixel electrode directly contacts the capacitor second electrode through a via-hole in the third insulating layer.

16. The flat panel display apparatus as claimed in claim 1, wherein the pixel electrode is a transparent electrode.

17. The flat panel display apparatus as claimed in claim 1, further comprising an opposite electrode facing the pixel electrode, wherein liquid crystals are present between the pixel electrode and the opposite electrode.

18. The flat panel display apparatus as claimed in claim 17, wherein a common voltage Vcom, a gate high signal Vgh, or gate low signal Vgl is applied to the capacitor first electrode.

19. The flat panel display apparatus as claimed in claim 1, further comprising an opposite electrode facing the pixel electrode, wherein an organic emission layer is formed between the pixel electrode and the opposite electrode.

20. A method of manufacturing a flat panel display apparatus, the method comprising:

forming a gate electrode of a thin film transistor and a capacitor first electrode on a substrate using a first mask;

forming a semiconductor layer of the thin film transistor and a capacitor second electrode using a second mask, wherein the semiconductor layer and the capacitor second electrode are separated from the gate electrode and the capacitor first electrode by a first insulating layer;

forming, using a third mask, a second insulating layer and contact holes exposing a portion of the semiconductor layer and a portion of the capacitor second electrode through the second insulating layer;

forming, using a fourth mask, source and drain electrodes connected to the semiconductor layer and the capacitor second electrode via the contact holes;

forming a third insulating layer and a via-hole using a fifth mask; and

forming a pixel electrode connected to any one of the source and drain electrodes via the via-hole using a sixth mask.

21. The method as claimed in claim 20, wherein the gate electrode includes a transparent conductive layer and a metallic layer disposed on the transparent conductive layer, and using the first mask, the capacitor first electrode and the transparent conductive layer are formed on a same plane and including a same material.

22. The method as claimed in claim 21, wherein the first mask includes a half-tone mask including a light-transmission portion, a semi-transmission portion corresponding to the capacitor first electrode, and a light-blocking portion corresponding to the gate electrode.

23. The method as claimed in claim 20, wherein each of the semiconductor layer and the capacitor second electrode includes a transparent conductive oxide.

24. The method as claimed in claim 20, further comprising removing a portion of the second insulating layer corresponding to the capacitor second using the third mask.

25. The method as claimed in claim 24, further comprising forming a capacitor third electrode on a portion of the substrate corresponding to the removed portion of the second insulating layer, and includes a same material as the source and drain electrodes.