MOTHER SUBSTRATE, ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

• US 20110309380A1
• Filed: 06/15/2011
• Published: 12/22/2011
• Est. Priority Date: 06/21/2010
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: XIAO, Hongxi, WU, Ping, LIU, Huafeng, SU, Shunkang, DING, Hanting
• Granted Patent: US 8,482,006 B2
• Time in Patent Office: Days
• US Class Current: 257/88
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

The present invention relates to a mother substrate and a method for manufacturing the same, the mother substrate comprising: a substrate, comprising at least one display region and pre-cutting regions in a periphery of the display region, wherein the display region comprises gate scanning lines and data scanning lines, the pre-cutting regions comprise a gate-line connecting line and a data-line connecting line electrically connected to each other, and the gate-line connecting line is electrically connected to all of the gate scanning lines in the display region, and the data-line connecting line is electrically connected to all of the data scanning lines in the display region substrate.

Claims

1. A mother substrate comprising:

a substrate;

comprising at least one display region and pre-cutting regions in a periphery of the display region,

wherein the display region comprises gate scanning lines and data scanning lines, the pre-cutting regions comprise a gate-line connecting line and a data-line connecting line electrically connected to each other, and

the gate-line connecting line is electrically connected to all of the gate scanning lines in the display region, and the data-line connecting line is electrically connected to all of the data scanning lines in the display region.

2. The mother substrate as claimed in claim 1, wherein both the gate-line connecting line and the data-line connecting line are located at the same layer as the gate scanning lines, the gate-line connecting line and the data-line connecting line are directly and electrically connected, the gate-line connecting line is in direct electric connection with the gate scanning lines in the display region, and

the data-line connecting line is electrically connected to the data scanning lines of the display region via through holes.

3. The mother substrate as claimed in claim 1, wherein both the gate-line connecting line and the data-line connecting line are located at the same layer as the data scanning lines, the gate-line connecting line and the data-line connecting line are directly and electrically connected, the data-line connecting line is in direct electric connection with the data scanning lines in the display region, and

the gate-line connecting line is electrically connected to the gate scanning lines of the display region via through holes.

4. The mother substrate as claimed in claim 1, wherein the gate-line connecting line and the gate scanning lines are located at one same layer, and the gate-line connecting line is in direct electric connection with the gate scanning lines of the display region;

the data-line connecting line and the data scanning lines are located at another same layer, and the data-line connecting line is in direct electric connection with the data scanning lines of the display region; and

the gate-line connecting line and the data-line connecting line are electrically connected via a through hole.

5. The mother substrate as claimed in claim 1, wherein the gate-line connecting line is located in the pre-cutting region at one side opposite to a gate scanning line PAD region, and the data-line connecting line is located in the pre-cutting region at one side opposite to a data scanning line PAD region.

6. The mother substrate as claimed in claim 1, wherein before the mother substrate is tested, the gate scanning lines are electrically disconnected with the gate-line connecting line, and the data scanning lines are electrically disconnected with the data-line connecting line.

7. The mother substrate as claimed in claim 6, wherein a disconnection region of the data scanning line is located at a position where one data scanning line and the data-line connecting line are electrically connected, or located at a position which is shifted a predetermined distance from the position, where the data scanning line and the data-line connecting line are electrically connected, towards the data scanning line, and

a disconnection region of the gate scanning line is located at a position where one gate scanning line and the gate-line connecting line are electrically connected, or located at a position which is shifted a predetermined distance from the position, where the gate scanning line and the gate-line connecting line are electrically connected, towards the gate scanning line.

8. A method for manufacturing a mother substrate for an array substrate, the mother substrate comprising at least one display region and pre-cutting regions in a periphery of the display region, the method comprising:

forming gate scanning lines and data scanning lines in the display region and forming a gate-line connecting line and a data-line connecting line electrically connected to each other in the pre-cutting regions,

wherein the gate-line connecting line is electrically connected to all of the gate scanning lines in the display region, and the data-line connecting line is electrically connected to all of the data scanning lines in the display region.

9. The method as claimed in claim 8, wherein forming the gate scanning lines and the data scanning lines in the display region and the forming the gate-line connecting line and the data-line connecting line electrically connected to each other in the pre-cutting region comprises:

(1) depositing a gate metal layer on a substrate with the at least one display region;

(2) patterning the gate metal layer to form a gate pattern comprising the gate scanning lines, gate electrodes connected to the gate scanning lines, and the gate-line connecting line and the data-line connecting line located at two adjacent sides of each display region, and retaining photoresist parts on the data-line connecting line at intersections of the data-line connecting line and the data scanning lines to be formed, wherein the gate-line connecting line is in direct electric connection with both the data-line connecting line and the gate scanning lines;

(3) sequentially depositing a gate insulating thin film and an active thin film on the substrate with the gate pattern;

(4) patterning the active thin film to form an active thin film pattern overlapping with the gate electrodes, lifting-off the pre-retained photoresist parts and removing the gate insulating thin film and the active thin film corresponding to the pre-retained photoresist parts; and

(5) forming the data scanning lines intersected with the gate scanning lines and source/drain electrodes of thin film transistors on the substrate with the active thin film pattern, wherein the data scanning lines extend to the positions of the pre-retained photoresist parts and are electrically connected to the data-line connecting line.

10. The method as claimed in claim 8, wherein forming the gate scanning lines and the data scanning lines in the display region and the forming the gate-line connecting line and the data-line connecting line electrically connected to each other in the pre-cutting region comprises:

(1) depositing a gate metal layer on a substrate with the at least one display region;

(2) patterning the gate metal layer to form a gate pattern comprising the gate scanning lines and gate electrodes connected with the gate scanning lines, and retaining photoresist parts on the gate scanning lines at intersections of the gate-line connecting line to be formed and the gate scanning lines;

(3) sequentially depositing a gate insulating thin film and an active thin film on the substrate with the gate pattern;

(4) patterning the active thin film to form an active thin film pattern overlapping with the gate, lifting-off the pre-retained photoresist parts and removing the gate insulating thin film and the active thin film corresponding to the pre-retained photoresist parts; and

(5) forming the data scanning lines intersected with the gate scanning lines, source/drain electrodes of thin film transistors, and the gate-line connecting line and the data-line connecting line located at two adjacent sides of each display region on the substrate with the active thin film pattern, wherein the gate-line connecting line is electrically connected to the gate scanning lines at positions of the pre-retained photoresist parts, and the data-line connecting line is in direct electric connection with both the gate-line connecting line and the data scanning lines.

11. The method as claimed in claim 8, wherein forming the gate scanning lines and the data scanning lines in the display region and the forming the gate-line connecting line and the data-line connecting line electrically connected to each other in the pre-cutting region comprises:

(1) depositing a gate metal layer on a substrate with the at least one display region;

(2) patterning the gate metal layer to form a gate pattern comprising the gate scanning lines, gate electrodes connected with the gate scanning lines, and the gate-line connecting line located at one side of each display region, and retaining a photoresist part on the gate-line connecting line at intersection of the gate-line connecting line and the data-line connecting line to be formed, and the gate-line connecting line is in direct electric connection with the gate scanning lines;

(3) sequentially depositing a gate insulating thin film and an active thin film on the substrate with the gate pattern;

(4) patterning the active thin film to form an active thin film pattern overlapping with the gate, lifting-off the pre-retained photoresist part and removing the gate insulating thin film and the active thin film corresponding to the pre-retained photoresist part; and

(5) forming the data scanning lines intersected with the gate scanning lines, source/drain electrodes of thin film transistors, and the data-line connecting line located at one side adjacent to the gate-line connecting line of each display region on the substrate with the active thin film pattern, wherein the data-line connecting line extends to the position of the pre-retained photoresist part and is electrically connected to the gate-line connecting line, and the data-line connecting line is in direct electric connection with the data scanning lines.

12. The method as claimed in claim 8, further comprising:

depositing a passivation layer, and performing a patterning process to form through holes at ends, electrically connected to the gate-line connecting line, of the gate scanning lines so as to expose the gate scanning lines and to form through holes at ends, electrically connected to the data-line connecting line, of the data scanning lines so as to expose the data scanning lines; and

removing portions of the data scanning lines and the gate scanning lines exposed through the through holes by using an etching process to form disconnection regions.

13. The method as claimed in claim 12, wherein the disconnection region of one data scanning line is located at a position where the data scanning line is electrically connected to the data-line connecting line, or at a position which is shifted a predetermined distance from the position, where the data scanning line and the data-line connecting line are electrically connected, towards the data scanning line, and

the disconnection region of one gate scanning line is located at a position where the gate scanning line is electrically connected to the gate-line connecting line, or at a position which is shifted a predetermined distance from the position, where the gate scanning line and the gate-line connecting line are electrically connected, towards the gate scanning line.