ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME

• US 20110309421A1
• Filed: 06/21/2010
• Published: 12/22/2011
• Est. Priority Date: 06/21/2010
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Kilopass Technology Incorporated (Synopsys Incorporated)
• Inventors: Luan, Harry S., He, Yue-Song, Wong, Ting-Wah
• Granted Patent: US 8,330,189 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.

Claims

1. An antifuse-based one-time programmable non-volatile memory cell comprising:

a buried bitline formed in a substrate, the buried bitline of a first conductivity type;

a dielectric layer formed over at least a portion of the buried bitline; and

a conductive gate formed over the dielectric layer, the conductive gate defining a channel region under the conductive gate and dielectric layer;

wherein the channel region does not have electrical interaction other than to said buried bitline or conductive gate.

2. The memory cell of claim 1 wherein formed on the sidewalls of the conductive gate are sidewall spacers.

3. The memory cell of claim 2 wherein floating regions of a second conductivity type are formed in the substrate spaced away from the channel region by the sidewall spacers.

4. The memory cell of claim 2 wherein regions of higher dopant concentration of the first conductivity type are formed in the bitline spaced away from the channel region by the sidewall spacers.

5. The memory cell of claim 1 wherein the buried bitline has a graded dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

6. The memory cell of claim 1 wherein said dielectric layer is thicker proximal to at least a portion of the edge of the channel region than to the center of the channel region.

7. The memory cell of claim 1 wherein the buried bitline is formed from standard n-well implants.

11. The memory cell of claim 7 wherein regions of higher dopant concentration of the first conductivity type are formed in the bitline spaced away from the channel region by the sidewall spacers.

8. A memory array comprised of a plurality of antifuse-based one-time programmable non-volatile memory cells, the memory array comprising:

a plurality of buried bitlines formed in a substrate, the buried bitline of a first conductivity type;

a dielectric layer formed over at least a portion of the buried bitlines; and

a plurality of conductive gate wordlines formed over the dielectric layer, the conductive gate wordlines intersecting with the plurality of buried bitlines, the memory cells located at the intersection of said conductive gate wordlines and buried bitlines, further wherein a channel region is defined under the intersection of said conductive gate wordlines and buried bitlines and dielectric layer;

wherein the channel region does not have electrical interaction other than to said buried bitline or conductive gate.

9. The memory array of claim 8 wherein formed on the sidewalls of the conductive gate of the memory cells are sidewall spacers.

10. The memory array of claim 9 wherein floating regions of a second conductivity type are formed in the substrate spaced away from the channel region by the sidewall spacers.

12. The memory array of claim 8 wherein the buried bitlines have a graded dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

13. The memory array of claim 8 wherein said dielectric layer is thicker proximal to at least a portion of the edge of the channel region than to the center of the channel region.

14. The memory array of claim 9 wherein the sidewall spacers of adjacent conductive gate wordlines completely span the space between the adjacent gate wordlines.

15. The memory array of claim 8 wherein shallow trench isolations are formed between the buried bitlines.

16. The memory array of claim 8 wherein buried bitlines are formed from standard n-well implants.