ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME
First Claim
Patent Images
1. An antifuse-based one-time programmable non-volatile memory cell comprising:
- a buried bitline formed in a substrate, the buried bitline of a first conductivity type;
a dielectric layer formed over at least a portion of the buried bitline; and
a conductive gate formed over the dielectric layer, the conductive gate defining a channel region under the conductive gate and dielectric layer;
wherein the channel region does not have electrical interaction other than to said buried bitline or conductive gate.
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Abstract
A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.
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Citations
16 Claims
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1. An antifuse-based one-time programmable non-volatile memory cell comprising:
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a buried bitline formed in a substrate, the buried bitline of a first conductivity type; a dielectric layer formed over at least a portion of the buried bitline; and a conductive gate formed over the dielectric layer, the conductive gate defining a channel region under the conductive gate and dielectric layer; wherein the channel region does not have electrical interaction other than to said buried bitline or conductive gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 11)
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8. A memory array comprised of a plurality of antifuse-based one-time programmable non-volatile memory cells, the memory array comprising:
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a plurality of buried bitlines formed in a substrate, the buried bitline of a first conductivity type; a dielectric layer formed over at least a portion of the buried bitlines; and a plurality of conductive gate wordlines formed over the dielectric layer, the conductive gate wordlines intersecting with the plurality of buried bitlines, the memory cells located at the intersection of said conductive gate wordlines and buried bitlines, further wherein a channel region is defined under the intersection of said conductive gate wordlines and buried bitlines and dielectric layer; wherein the channel region does not have electrical interaction other than to said buried bitline or conductive gate. - View Dependent Claims (9, 10, 12, 13, 14, 15, 16)
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Specification