Air Gap Isolation In Non-Volatile Memory
First Claim
1. A non-volatile memory array, comprising:
- a first column of non-volatile storage elements formed over a first active area of a substrate;
a second column of non-volatile storage elements formed over a second active area of the substrate;
an isolation region in the substrate between the first active area and the second active area;
a bit line air gap in the isolation region; and
a cap extending in the row direction between a first charge storage region of the first column and a first charge storage region of the second column, the cap extending vertically with respect to a surface of the substrate along at least a portion of the first charge storage region and the second charge storage region.
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Abstract
Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.
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Citations
32 Claims
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1. A non-volatile memory array, comprising:
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a first column of non-volatile storage elements formed over a first active area of a substrate; a second column of non-volatile storage elements formed over a second active area of the substrate; an isolation region in the substrate between the first active area and the second active area; a bit line air gap in the isolation region; and a cap extending in the row direction between a first charge storage region of the first column and a first charge storage region of the second column, the cap extending vertically with respect to a surface of the substrate along at least a portion of the first charge storage region and the second charge storage region. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating non-volatile storage, comprising:
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forming a first layer stack column and a second layer stack column elongated in a column direction over a substrate, each layer stack column having two vertical sidewalls and including a charge storage strip over a tunnel dielectric strip, the first layer stack column overlying a first active area of the substrate and the second layer stack column overlying a second active area of the substrate; etching the substrate to define an isolation region between the first active area and the second active area; growing a cap between the first layer stack column and the second layer stack column, the cap extending vertically along at least a portion of the charge storage strip of the first column and the charge storage strip of the second column; and forming a bit line air gap in the isolation region having an upper endpoint defined at least partially by the cap. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A non-volatile memory array, comprising:
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a plurality of non-volatile storage elements arranged into rows and columns above a surface of a substrate; a plurality of isolation regions formed in the substrate between active areas of the substrate that underlie adjacent columns of non-volatile storage elements, each non-volatile storage element including a charge storage region; a plurality of bit line air gaps formed in the plurality of isolation regions; a plurality of air gap caps including at least one air gap cap overlying air within each isolation region, the at least one air gap extending vertically with respect to a surface of the substrate to at least a level of a lower surface of the charge storage regions of the adjacent column; and a plurality of word line air gaps formed at least partially between adjacent rows of non-volatile storage elements.
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- 29. A non-volatile memory array according to claim 29, wherein the plurality of air gap caps includes a single air gap cap for each isolation region.
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31. A non-volatile memory array according to claim 31, wherein:
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the plurality of bit line air gaps includes a set of two or more air gap caps overlying each isolation region; the set of two or more air gap caps have lower surfaces defining an upper endpoint for a first portion of the corresponding underlying air gap; and the lower surface of each word line air gap defines an upper endpoint region for a second portion of the corresponding underlying air gap.
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32. A non-volatile memory array, comprising:
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an array of non-volatile storage elements arranged into a plurality of rows and a plurality of columns over a substrate, the plurality of columns overlying a plurality of active areas in the substrate, each non-volatile storage element including a charge storage region; a plurality of isolation regions in the substrate between adjacent active areas; a plurality of bit line air gaps formed in the plurality of isolation regions; a plurality of caps overlying the plurality of isolation regions, each cap overlying a corresponding isolation region to define an upper endpoint for at least a portion of the air gap formed in the corresponding isolation region, each cap extending vertically with respect to a surface of the substrate along at least a portion of an adjacent charge storage region.
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Specification