Air Gap Isolation In Non-Volatile Memory

• US 20110309425A1
• Filed: 06/16/2011
• Published: 12/22/2011
• Est. Priority Date: 06/19/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Purayath, Vinod Robert, Matamis, George, Harari, Eli, Kinoshita, Hiroyuki, Pham, Tuan
• Granted Patent: US 8,603,890 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.

Claims

1. A non-volatile memory array, comprising:

a first column of non-volatile storage elements formed over a first active area of a substrate;

a second column of non-volatile storage elements formed over a second active area of the substrate;

an isolation region in the substrate between the first active area and the second active area;

a bit line air gap in the isolation region; and

a cap extending in the row direction between a first charge storage region of the first column and a first charge storage region of the second column, the cap extending vertically with respect to a surface of the substrate along at least a portion of the first charge storage region and the second charge storage region.

2. A non-volatile memory array according to claim 1, wherein:

each charge storage region overlies a tunnel dielectric material;

the cap extends vertically along at least a portion of the tunnel dielectric material underlying the first charge storage region.

3. A non-volatile memory array according to claim 1, further comprising:

a first row of non-volatile storage elements extending in a row direction across the substrate surface, the row direction being perpendicular to the column direction, the first row including a first non-volatile storage element of the first column, a first non-volatile storage element of the second column and a first control gate extending in the row direction, the first control gate being shared by the first non-volatile storage elements of the first and second columns;

a second row of non-volatile storage elements extending in the row direction across the substrate surface, the second row including a second non-volatile storage element of the first column, a second non-volatile storage element of the second column and a second control gate extending in the row direction, the second control gate being shared by the second non-volatile storage elements of the first and second columns; and

a word line air gap elongated in the row direction and extending in the column direction at least a portion of a distance between the first row and the second row.

4. A non-volatile memory array according to claim 3, wherein:

the cap is a first cap of a plurality of caps of the non-volatile memory array;

the first column includes a first plurality of charge storage regions adjacent in a column direction;

the second column includes a second plurality of charge storage regions adjacent in the column direction;

each cap of the plurality extends in a row direction between one charge storage region of the first column and one charge storage region of the second column, each cap extending vertically with respect to the surface of the substrate along at least a portion of the corresponding charge storage regions, wherein a lower surface of each cap forms an upper endpoint for at least a portion of the bit line air gap.

5. A non-volatile memory array according to claim 4, further comprising:

a capping strip overlying the word line air gap, the capping strip having a lower surface that forms an upper endpoint region for at least a second portion of the bit line air gap.

6. A non-volatile memory according to claim 1, further comprising:

a catalyst layer formed along a vertical sidewall of the first charge storage region.

7. A method of fabricating non-volatile storage, comprising:

forming a first layer stack column and a second layer stack column elongated in a column direction over a substrate, each layer stack column having two vertical sidewalls and including a charge storage strip over a tunnel dielectric strip, the first layer stack column overlying a first active area of the substrate and the second layer stack column overlying a second active area of the substrate;

etching the substrate to define an isolation region between the first active area and the second active area;

growing a cap between the first layer stack column and the second layer stack column, the cap extending vertically along at least a portion of the charge storage strip of the first column and the charge storage strip of the second column; and

forming a bit line air gap in the isolation region having an upper endpoint defined at least partially by the cap.

8. A method according to claim 7, further comprising:

forming a catalyst layer along at least a portion of the two vertical sidewalls of each layer stack column prior to etching the substrate;

9. A method according to claim 8, wherein growing the cap between the first layer stack column and the second layer stack column includes:

selectively growing the cap using the catalyst layer to form the cap between the charge storage strip of the first layer stack column and the charge storage strip of the second layer stack column.

10. A method according to claim 9, wherein:

selectively growing the cap using the catalyst layer includes pulsed layer deposition.

11. A method according to claim 7, further comprising:

modifying a surface of at least a portion of the two vertical sidewalls of each layer stack column by ion implantation prior to etching the substrate.

12. A method according to claim 11, wherein growing the cap between the first layer stack column and the second layer stack column includes:

selectively growing the cap using the modified surface of the two vertical sidewalls to form the cap between the charge storage strip of the first layer stack column and the charge storage strip of the second layer stack column.

13. A method according to claim 11, wherein selectively growing the cap includes:

providing ozone and tetraethyl orthosilicate in a first ratio to form a nucleation layer on the modified surface of the two vertical sidewalls; and

changing the ratio of the ozone to the tetraethyl orthosilicate to induce selective growth of the cap along the nucleation layer.

14. A method according to claim 7, wherein:

etching the substrate is performed prior to forming the first layer stack column and the second layer stack column;

the isolation region is a first isolation region;

the method further comprises forming a second isolation region and a third isolation region in the substrate, the second isolation region being adjacent to the first active area and a fourth active area and the third isolation region being adjacent to the second active area and a fifth active area.

15. A method according to claim 14, further comprising:

forming an isolation material in each isolation region, the isolation material including a first protrusion extending above the substrate surface from the first isolation region, a second protrusion extending above the substrate surface from the second isolation region and a third protrusion extending above the substrate surface from the third isolation region;

slimming a dimension of each protrusion in the row direction;

forming the charge storage strip for the first column by depositing charge storage material between the first protrusion and the second protrusion; and

forming the charge storage strip for the second column by depositing charge storage material between the first protrusion and the third protrusion.

16. A method according to claim 15, wherein:

the charge storage strip for the first column has a first vertical sidewall that overlies the second isolation region and a second vertical sidewall that overlies the first isolation region;

the charge storage strip for the second column has a first vertical sidewall that overlies the first isolation region and a second vertical sidewall that overlies the third isolation region.

17. A method according to claim 16, further comprising:

removing the protrusions and recessing the isolation material below a level of the substrate surface after forming each charge storage strip.

18. A method according to claim 17, wherein:

growing the cap between the first layer stack column and the second layer stack column includes thermally oxidizing at least a portion of the second vertical sidewall of the charge storage strip for the first column and the first vertical sidewall of the charge storage strip for the second column to grow the cap between the first and second charge storage strips;

the cap includes oxide that grows from the second vertical sidewall of the charge storage strip for the first column and oxide that grows that grows from the first vertical sidewall of the charge storage strip for the second column, the oxides meeting above the first isolation region and at least partially overlying air to from the bit line air gap in the first isolation region.

19. A method according to claim 7, further comprising:

recessing the cap below a level of an upper surface of the charge storage strips;

forming an intermediate dielectric layer over the upper surface and along the vertical sidewalls of the charge storage strips; and

forming a control gate layer over the intermediate dielectric layer, the control gate layer extending below the upper surface of the charge storage strips between adjacent portions of the intermediate dielectric layer.

20. A method according to claim 19, further comprising:

etching the control gate layer into a plurality of control gates;

etching the charge storage strip for the first column into a first plurality of charge storage regions;

etching the charge storage strip for the second column into a second plurality of charge storage regions;

wherein the plurality of control gates includes a first control gate separated from a first charge storage region of the first plurality and a first charge storage region of the second plurality;

wherein the plurality of control gates includes a second control gate separated from a second charge storage region of the first plurality and a second charge storage region of the second plurality.

21. A method according to claim 20, wherein:

etching the control gate layer, the charge storage strip for the first column and the charge storage strip for the second column is orthogonal to a direction of the first layer stack column and the second layer stack column.

22. A method according to claim 21, wherein:

etching the control gate layer, the charge storage strip for the first column and the charge storage strip for the second column forms a plurality of layer stack rows including a first layer stack row and a second layer stack row;

the first layer stack row includes the first control gate, a first intermediate dielectric strip, and the first plurality of charge storage regions; and

the second layer stack row includes the second control gate, a second intermediate dielectric strip, and the second plurality of charge storage regions.

23. A method according to claim 22, further comprising:

forming a plurality of word line air gaps including a first word line air gap formed between the first layer stack row and the second layer stack row.

24. A method according to claim 23, wherein:

the first word line air gap extends vertically, with respect to the substrate surface, from a level above the substrate surface to at least a level of an upper surface of the first and second control gate.

25. A method according to claim 24, further comprising, after etching the control gate layer and before etching the charge storage strip for the first column and the charge storage strip for the second column:

forming a catalytic layer on a first and a second sidewall of each control gate.

26. A method according to claim 25, further comprising, after etching the charge storage strip for the first column and the charge storage strip for the second column and before forming the plurality of word line air gaps:

selectively growing a temporary cap between each pair of adjacent control gates;

recessing the temporary caps below an upper surface of each control gate;

siliciding the control gates after recessing the temporary caps.

27. A method according to claim 26, further comprising:

removing the temporary caps after siliciding the control gates;

nonconformally depositing a capping layer to form permanent word line air gap caps that overlie air between adjacent layer stack rows, the permanent word line air gap caps defining an upper endpoint of the corresponding word line air gap.

28. A non-volatile memory array, comprising:

a plurality of non-volatile storage elements arranged into rows and columns above a surface of a substrate;

a plurality of isolation regions formed in the substrate between active areas of the substrate that underlie adjacent columns of non-volatile storage elements, each non-volatile storage element including a charge storage region;

a plurality of bit line air gaps formed in the plurality of isolation regions;

a plurality of air gap caps including at least one air gap cap overlying air within each isolation region, the at least one air gap extending vertically with respect to a surface of the substrate to at least a level of a lower surface of the charge storage regions of the adjacent column; and

a plurality of word line air gaps formed at least partially between adjacent rows of non-volatile storage elements.

29. A non-volatile memory array according to claim 29, wherein the plurality of air gap caps includes a single air gap cap for each isolation region.

30. A non-volatile memory array according to claim 29, wherein the plurality of air gap caps is a plurality of bit line air gap caps, the non-volatile memory array further comprising:

a plurality of word line air gap caps including one word line cap overlying each air gap of the second plurality, a lower surface of each word line air gap defining an upper endpoint for the corresponding underlying word line air gap.

31. A non-volatile memory array according to claim 31, wherein:

the plurality of bit line air gaps includes a set of two or more air gap caps overlying each isolation region;

the set of two or more air gap caps have lower surfaces defining an upper endpoint for a first portion of the corresponding underlying air gap; and

the lower surface of each word line air gap defines an upper endpoint region for a second portion of the corresponding underlying air gap.

32. A non-volatile memory array, comprising:

an array of non-volatile storage elements arranged into a plurality of rows and a plurality of columns over a substrate, the plurality of columns overlying a plurality of active areas in the substrate, each non-volatile storage element including a charge storage region;

a plurality of isolation regions in the substrate between adjacent active areas;

a plurality of bit line air gaps formed in the plurality of isolation regions;

a plurality of caps overlying the plurality of isolation regions, each cap overlying a corresponding isolation region to define an upper endpoint for at least a portion of the air gap formed in the corresponding isolation region, each cap extending vertically with respect to a surface of the substrate along at least a portion of an adjacent charge storage region.