SEMICONDUCTOR DEVICE INCLUDING CELL REGION AND PERIPHERAL REGION HAVING HIGH BREAKDOWN VOLTAGE STRUCTURE

• US 20110309464A1
• Filed: 06/20/2011
• Published: 12/22/2011
• Est. Priority Date: 06/22/2010
• Status: Active Grant

• Current Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Suzuki, Naohiro, Takaya, Hidefumi, Sugimoto, Masahiro, Morimoto, Jun, Soejima, Narumasa, Ishikawa, Tsuyoshi, Watanabe, Yukihiko, YAMAMOTO, Kensaku
• Granted Patent: US 8,492,867 B2
• Time in Patent Office: Days
• US Class Current: 257/493
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate including a substrate, a drift layer of a first conductivity type disposed on a surface of the substrate, and a base layer of a second conductivity type disposed on a surface of the drift layer; and

an electric field terminal part, wherein

the semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region,

the base region has a bottom face located on a same plane throughout the cell region and the peripheral region,

a portion of the base region located in the peripheral region provides an electric field relaxing layer,

the electric field terminal part is disposed in the peripheral region,

the electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer, and

the electric field terminal part penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.

2. The semiconductor device according to claim 1, wherein

the electric field terminal part includes at least one groove penetrating the electric field relaxing layer from the surface of the electric field relaxing layer to the drift layer and an insulating member disposed in the at least one groove.

3. The semiconductor device according to claim 2, wherein

the at least one groove includes a plurality of grooves,

the insulating member is disposed in each of the plurality of grooves, and

the plurality of grooves concentrically surrounds the cell region and the portion of the electric field relaxing layer.

4. The semiconductor device according to claim 1, wherein

the electric field terminal part includes a first conductivity type layer that penetrates the electric field relaxing layer from the surface of the electric field relaxing layer to the drift layer.

5. The semiconductor device according to claim 1, wherein

the semiconductor substrate has a recess section in the peripheral region,

the recess section is formed by removing a portion of the base layer from a surface of the base layer so as to form a mesa structure, and

the electric field terminal part is disposed in the recess section.

6. The semiconductor device according to claim 1, wherein

the semiconductor substrate has a recess section in the peripheral region,

the recess section is formed by removing a portion of the base layer from a surface of the base layer so as to form a mesa structure, and

the electric field terminal part is disposed outside the recess section.

7. The semiconductor device according to claim 5, wherein

the recess section has a stepped portion adjacent to the cell region, and the electric field terminal part is located at a distance of from 1 μ

m to 1000 μ

m from the stepped portion.

8. The semiconductor device according to claim 1, wherein

the base layer and the electric field relaxing layer have an impurity concentration of from 1×

10¹⁶ cm<sup>−

3</sup> to 2.5×

10¹⁷ cm<sup>−

3</sup>.