Trench MOS Barrier Schottky Rectifier With A Planar Surface Using CMP Techniques

• US 20110309470A1
• Filed: 06/18/2010
• Published: 12/22/2011
• Est. Priority Date: 06/18/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Grebs, Thomas E.
• Granted Patent: US 8,319,290 B2
• Time in Patent Office: Days
• US Class Current: 257/520
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Claims

1-9. -9. (canceled)

10. A method of forming a semiconductor device, comprising:

forming a field oxide in an epitaxial layer;

wherein the field oxide extends into the epitaxial layer and above the epitaxial layer;

planarizing the field oxide using chemical mechanical planarization (CMP) to generate a substantially planar surface comprising substantially planar regions of field oxide and epitaxial layer;

forming a plurality of trenches in the epitaxial layer separated by mesas, the plurality of trenches comprising sidewalls and a bottom;

forming a shield dielectric that lines the sidewalls and bottom of the trenches and substantially covers the mesas and field oxide region;

depositing polysilicon to substantially fill the plurality of trenches and substantially cover the shield dielectric.

11. The method of claim 10 further comprising planarizing the polysilicon using chemical mechanical planarization (CMP) to generate a substantially planar surface comprising substantially planar regions of polysilicon, shield dielectric, and mesas.

12. The method of claim 10 wherein forming the field oxide comprises:

forming a pad oxide layer over a substrate;

forming a nitride layer over the pad oxide layer;

etching the pad oxide layer and nitride layer, according to a pattern;

gowning the field oxide in the pattern and recessed into the substrate; and

removing the pad oxide layer and nitride layer from active areas.

13. A method of forming a semiconductor device, comprising:

forming a field oxide in an epitaxial layer;

wherein the field oxide extends into the epitaxial layer and above the epitaxial layer;

forming a plurality of trenches in the epitaxial layer separated by mesas, the plurality of trenches comprising sidewalls and a bottom;

forming a shield dielectric that lines the sidewalls and bottom of the trenches and substantially covers the mesas and field oxide region;

depositing polysilicon to substantially fill the plurality of trenches and substantially cover the shield dielectric;

forming a top metal over the polysilicon and over a portion of the shield dielectric layer;

forming a dielectric layer over a first portion of the top metal;

forming a solderable top metal (STM) layer over a second portion of the top metal; and

planarizing the STM layer using chemical mechanical planarization (CMP) to generate a substantially planar surface comprising substantially planar regions of the STM material and dielectric material.

14. The method of claim 13 further comprising planarizing the field oxide using chemical mechanical planarization (CMP) to generate a substantially planar surface comprising substantially planar regions of field oxide and epitaxial layer.

15. The method of claim 13 further comprising planarizing the polysilicon using chemical mechanical planarization (CMP) to generate a substantially planar surface comprising substantially planar regions of polysilicon, shield dielectric and mesas.

16. The method of claim 13 further comprising:

planarizing the field oxide using chemical mechanical planarization (CMP) to generate a substantially planar surface comprising substantially planar regions of field oxide and epitaxial layer; and

planarizing the polysilicon using chemical mechanical planarization (CMP) to generate a substantially planar surface comprising substantially planar regions of polysilicon, shield dielectric and mesas.

17. The method of claim 13 further comprising forming a nickel silicide (NiSi) layer over the plurality of trenches.

18. The method of claim 17 wherein the top metal is formed over a portion of the NiSi layer and over a portion of the shield dielectric layer deposited on the field oxide layer.

19. The method of claim 13 wherein the dielectric layer comprise polyimide.

20-23. -23. (canceled)

24. A semiconductor device comprising:

an epitaxial layer;

a field oxide region disposed in the epitaxial layer, wherein the field oxide extends into the epitaxial layer and forms a substantially planar first surface comprising substantially planar regions of field oxide and epitaxial layer;

a plurality of trenches comprising sidewalls and a bottom disposed in the epitaxial layer, the plurality of trenches separated by a plurality of mesas;

a shield dielectric that lines the trench sidewalls and bottom of the trenches and covers the field oxide region; and

a polysilicon that substantially fills the plurality of trenches.

25. The semiconductor device of claim 24 wherein the first surface is formed using chemical mechanical planarization (CMP).

26. The semiconductor device of claim 24 wherein the top surface of the field oxide and the top surface of the epitaxial layer form a contiguous surface.

27. The semiconductor device of claim 24 further comprising a substantially planar second surface comprising substantially planar regions of polysilicon, shield dielectric and mesas, the second surface is formed using CMP.

28. A semiconductor device comprising:

an epitaxial layer;

a field oxide region disposed in the epitaxial layer, wherein the field oxide extends into the epitaxial layer;

a plurality of trenches comprising sidewalls and a bottom disposed in the epitaxial layer, the plurality of trenches separated by a plurality of mesas;

a shield dielectric that lines the trench sidewalls and bottom of the trenches and covers the field oxide region;

a polysilicon that substantially fills the plurality of trenches;

a top metal that covers a portion of the shield dielectric layer;

a dielectric layer that covers a first portion of the top metal;

a solderable top metal (STM) layer disposed adjacent to the dielectric layer and covering a second portion of the top metal; and

a substantially planar first surface comprising substantially planar regions of the STM material and dielectric material.

29. The semiconductor device of claim 28 wherein the substantially planar first surface is formed using chemical mechanical planarization (CMP).

30. The semiconductor device of claim 28 further comprising a substantially planar second surface comprising substantially planar regions of field oxide and epitaxial layer, the substantially planar second surface formed using chemical mechanical planarization (CMP).

31. The semiconductor device of claim 28 further comprising a substantially planar third surface comprising substantially planar regions of polysilicon, shield dielectric and mesas, the substantially planar third surface formed using chemical mechanical planarization (CMP).

32. The semiconductor device of claim 28 further comprising:

a substantially planar second surface comprising substantially planar regions of field oxide and epitaxial layer, the substantially planar second surface formed using chemical mechanical planarization (CMP); and

a substantially planar third surface comprising substantially planar regions of polysilicon, shield dielectric and mesas, the substantially planar third surface formed using chemical mechanical planarization (CMP).

33. The semiconductor device of claim 28 wherein the dielectric layer comprises polyimide.

34. The semiconductor device of claim 28 wherein the STM metal comprises Ti/NiV/Ag or Ta/Cu.