Pixel Circuit And Display Apparatus Including The Same

• US 20110310079A1
• Filed: 04/28/2011
• Published: 12/22/2011
• Est. Priority Date: 06/18/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jung-Woo, Jin, Yong-Wan
• Granted Patent: US 8,896,567 B2
• Time in Patent Office: Days
• US Class Current: 345/211
• CPC Class Codes: G06F 2203/04106 Multi-sensing digitiser, i.e. digitiser using at least two different sensing technologies simultaneously or alternatively, e.g. for detecting pen and finger, for saving power or for improving position detection
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04144 using an array of force sensing means position sensing using the local deformation of sensor cells G06F3/0447
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/042 by opto-electronic means
• CPC Class Codes: G09G 2300/0456 with a reflective area and a transmissive area combined in one pixel, such as in transflectance pixels
• CPC Class Codes: G09G 2300/088 using a non-linear two-terminal element
• CPC Class Codes: G09G 2380/14 Electronic books and readers
• CPC Class Codes: G09G 3/3433 using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices using liquid crystal devices G09G3/36; using electrochromic devices G09G3/38

Abstract

A pixel circuit includes a first transistor that supplies a data signal to a first node in response to a scan signal. The pixel circuit may also include a capacitor that is connected between the first node and a ground voltage and a detecting unit that is connected in parallel with the capacitor. More so, the detecting unit may change a voltage of the first node by being activated in response to a mode signal. Also, the detecting unit may have resistance that varies according to an external stimulus. The pixel circuit may also include a second transistor that is complementarily activated with respect to the detecting unit in response to the mode signal, and that provides a voltage of the first node.

Claims

1. A pixel circuit comprising:

a first transistor configured to supply a first signal to a first node in response to a second signal;

a capacitive unit connected between the first node and a ground voltage;

a detecting unit configured to change a voltage of the first node by being activated in response to a third signal, and the detecting unit having a resistance varying according to an external stimulus; and

a second transistor configure to provide a voltage of the first node to a display device in response to the third signal.

2. The pixel circuit of claim 1, wherein the detecting unit comprises:

a third transistor including a first terminal connected to the first node, and a gate configured to receive a detection control signal; and

a switch that electrically connects a second terminal of the third transistor and a ground voltage in response to the third signal.

3. The pixel circuit of claim 2, wherein the third transistor is a photo resistor with a resistance that varies according to an amount of light of the external stimulus.

4. The pixel circuit of claim 3, wherein the detection control signal has a voltage that is smaller than a threshold voltage value of the third transistor.

5. The pixel circuit of claim 1, wherein the detecting unit is a piezo resistor, and the resistance of the piezo resistor varies according to a pressure of the external stimulus.

6. The pixel circuit of claim 1, further comprising:

a determining unit configured to output a detection signal in response to the second signal, the detecting signal being based on the voltage of the first node.

7. The pixel circuit of claim 6, wherein the determining unit comprises:

an amplifier including,

a first terminal configured to receive the voltage of the first node, and

a second terminal configured to receive a reference voltage, amplify a voltage difference between the first terminal and the second terminal, and provide the detection signal to an output terminal, and

a feedback capacitor connected between the first terminal and the output terminal.

8. The pixel circuit of claim 1, wherein,

the display device is connected to the second transistor.

9. The pixel circuit of claim 8, wherein the display device is at least one of a liquid crystal display (LCD) device, a plasma display device, an organic electroluminescent device, and an electrophoretic device.

10. The pixel circuit of claim 8, wherein, if the third signal corresponds to a first logic state,

the second signal corresponds to an image signal, the second transistor is configured to provide the image signal to the display device in response to a selection signal, and the detecting unit is configured to deactivate .

11. The pixel circuit of claim 8, wherein, if the third signal corresponds to a second logic state,

the data signal has a first value, the detecting unit is configured to discharge charges stored in a capacitor, and the second transistor is deactivated, and wherein the capacitor is connected in parallel with the detecting unit.

12. The pixel circuit of claim 8, wherein the second transistor comprises:

a first terminal connected to the first node,

a gate receiving the third signal, and

a second node connected to the display device.

13. The pixel circuit of claim 8, wherein the second transistor comprises:

a second node connected to the display device,

a gate connected to the first node, and

a second terminal receiving the third signal.

14. A display apparatus comprising:

a control unit configured to generate a first control signal, a second control signal, and a mode signal;

a scan driver configured to generate a scan signal according to the second control signal;

a data driver configured to generate a first data signal according to the first control signal; and

a pixel array configured to configured to transfer the first data signal if the mode signal corresponds to a first logic state, and to provide the data driver with a second data signal if the mode signal corresponds to a second logic state, the second data signal being different than the first data signal, and the second data signal being based on an external stimulus.

15. The display apparatus of claim 14, wherein the pixel array comprises:

a plurality of scan lines configured to receive the scan signal;

a plurality of data lines configured to receive the data signal; and

a plurality of pixel circuits that are connected to the plurality of scan lines and the plurality of data lines, and each of the plurality of pixel circuits including,

a first transistor configured to supply the data signal to a first node in response to the scan signal,

a capacitor that is connected between the first node and a ground voltage,

a detecting unit that is connected between the first node and the ground voltage, and configured to change the data signal by being activated in response to the mode signal, and the detecting unit having a resistance value that varies according to the external stimulus,

a second transistor that is configured to provide a voltage of the first node in response to the mode signal, and

a display device configured to receive the voltage of the first node from the second transistor.

16. The display apparatus of claim 15, wherein the detecting unit includes a photo thin film transistor (TFT) and a piezo resistor that have resistances varying according to the external stimulus.

17. The display apparatus of claim 15, wherein the display device includes,

a first terminal configured to receive the voltage of the first node, and

a second terminal configured to receive an external voltage, and the display device is a reflective display device configured to display different images according to an electric field.

18. The display apparatus of claim 15, wherein the data driver includes a determining unit configured to generate a detection signal if the mode signal corresponds to the second logic state by comparing a reference voltage with the voltage of the first node after a time period elapses.

19. The display apparatus of claim 14, wherein, if the mode signal corresponds to the first logic state, the data signal is generated according to the detection signal.

20. The display apparatus of claim 14, wherein, if the mode signal corresponds to the second logic state, the data signal is deactivated after reaching a first value during an initialization period.