PROGRAMMING METHOD FOR NAND FLASH MEMORY DEVICE TO REDUCE ELECTRONS IN CHANNELS

• US 20110310666A1
• Filed: 04/30/2009
• Published: 12/22/2011
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: Powerchip Semiconductor Manufacturing Corp. (Powerchip Technology Corporation)
• Original Assignee: Powerchip Corporation, Powerchip Technology Corporation
• Inventors: Miida, Takashi, Shirota, Riichiro, Arakawa, Hideki, Yang, Ching Sung, Lin, Tzung Ling
• Granted Patent: US 8,599,614 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region

Abstract

In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

Claims

1. A programming method for a NAND flash memory device comprising a memory cell array formed on a P-well of a semiconductor substrate, the memory cell array including a plurality of cell strings connected to a plurality of word lines, the programming method including a step of reducing electrons in channel, source and drain regions of the cell strings before a step of programming a memory cell to be programmed.

2. The method as claimed in claim 1,

wherein the step of reducing the electrons includes a step of biasing the word lines to be a voltage lower than a bias voltage of the P-well to accumulate holes at a channel surface to ionize interface traps which recombine with electrons during a self boosting operation upon programming for inhibit cells.

3. The method as claimed in claim 2,

wherein the step of reducing includes a step of negatively biasing the word lines against the P-well.

4. The method as claimed in claim 3,

wherein the step of negatively biasing includes step of applying a negative voltage to the word lines with the P-well grounded.

5. The method as claimed in claim 2,

wherein the step of reducing includes a step of positively biasing the P-well against the word lines.

6. The method as claimed in claim 5,

wherein the step of positively biasing includes a step of applying a positive voltage to the P-well with the word lines grounded.

7. The method as claimed in claim 5,

wherein the step of positively biasing includes a step of applying a positive voltage to the P-well while applying a negative voltage to the word lines.

8. A programming method for a NAND flash memory device comprising a memory cell array formed on a P-well of a semiconductor substrate, the memory cell array including a plurality of cell strings connected to word lines and being divided into a plurality of blocks, each block corresponding to respective word lines selected from the word lines, the programming method including the steps of:

reducing channel electrons in the cell strings; and

applying a program voltage to at least one selected word line while applying one or several pass voltages Vpass in a range between OV and the program voltage, to deselected word lines after the step of reducing.

9. The method as claimed in claim 8,

wherein the step of reducing includes a step of negatively biasing the word lines against the P-well.

10. The method as claimed in claim 9,

wherein the step of negatively biasing includes step of applying a negative voltage to the word lines with the P-well grounded.

11. The method as claimed in claim 9,

wherein the word line which is negatively biased is only one word line connected to a memory cell to be programmed.

12. The method as claimed in claim 9,

wherein the step of negatively biasing includes a step of applying a negative voltage to a plurality of word lines in the memory string, which include one word line connected to a memory cell to be programmed.

13. The method as claimed in claim 9,

wherein the step of negatively biasing includes a step of applying a negative voltage to all the word lines in a selected block including a memory cell to be programmed.

14. The method as claimed in claim 9,

wherein the step of negatively biasing includes a step of applying a negative voltage to all the word lines in a plurality of selected blocks, one selected block including a memory cell to be programmed.

15. The method as claimed in claim 8,

wherein each cell string is connected to each bit line, and

wherein the method further includes the steps of:

applying a voltage corresponding to the program voltage to the bit line connected to a memory string to be programmed before the step of reducing the channel electrons; and

applying a voltage corresponding to a program inhibit voltage to the bit line connected to a memory string to be unprogrammed before the step of reducing the channel electrons.

16. The method as claimed in claim 8,

wherein each cell string is connected to each bit line, and

wherein the method further includes the steps of:

applying a voltage corresponding to a program inhibit voltage to the bit lines before the step of reducing the channel electrons; and

applying a voltage corresponding to the program voltage to the bit line connected to a memory string to be programmed at start of programming.

17. The method as claimed in claim 8,

wherein the step of reducing includes a step of positively biasing the P-well against the word lines in the memory string.

18. The method as claimed in claim 17,

wherein the step of positively biasing includes a step of applying a positive voltage to the P-well with the word lines in the memory string grounded.

19. The method as claimed in claim 17,

wherein the step of positively biasing includes a step of applying a positive voltage to the P-well while applying a negative voltage to the word lines in the memory string.

20. The method as claimed in claim 17, further including a step of grounding the P-well upon applying the program voltage.

21. The method as claimed in claim 17,

wherein the step of positively biasing the P-well against the word lines includes a step of applying a negative voltage to only one word line connected to a memory cell to be programmed.

22. The method as claimed in claim 17,

wherein the step of positively biasing includes a step of applying a negative voltage to a plurality of word lines in the memory string, which include one word line connected to a memory cell to be programmed.

23. The method as claimed in claim 17,

wherein the step of positively biasing includes a step of applying a negative voltage to a plurality of word line in the memory string, which include all the word lines in a selected block including a memory cell to be programmed.

24. The method as claimed in claim 17,

wherein the step of positively biasing includes a step of applying a negative voltage to a plurality of selected word lines, which include all the word lines in a plurality of selected blocks, one selected block including a memory cell to be programmed.

25. The method as claimed in claim 17, further including a step of setting the bit lines to a floating state upon positively biasing the P-well.

26. The method as claimed in claim 25, further including the steps of:

applying a voltage corresponding to the program voltage to the bit line including a memory cell to be programmed before the step of positively biasing the P-well; and

applying a voltage corresponding to a program inhibit voltage to the bit lines except for the bit line including the memory cell to be programmed before the step of positively biasing the P-well.

27. The method as claimed in claim 25, further including the steps of:

applying a voltage corresponding to the program voltage to the bit line including a memory cell to be programmed after the step of positively biasing the P-well; and

applying a voltage corresponding to a program inhibit voltage to the bit lines except for the bit line including the memory cell to be programmed after the step of positively biasing the P-well.

28. The method as claimed in claim 25, further including the steps of:

applying a voltage corresponding to a program inhibit voltage to the bit lines before the step of positively biasing the P-well; and

applying a voltage corresponding to the program voltage to the bit lines including the memory cell to be programmed upon programming the memory cell.

29. The method as claimed in claim 9,

wherein the step of negatively biasing the word lines against the P-well includes a step of changing a relative voltage to be biased to the selected word lines, against the P-well, in an order of a negative voltage before a first period, OV in the first period, the pass voltage Vpass in the second period, and the program voltage or the pass voltage Vpass in the third period.

30. The method as claimed in claim 9,

wherein the step of negatively biasing the word lines against the P-well includes a step of changing a relative voltage to be biased to the selected word lines, against the P-well, in an order of OV before a first period, a negative voltage in the first period, the pass voltage Vpass in the second period, and the program voltage or the pass voltage Vpass in the third period.

31. The method as claimed in claim 9,

wherein the step of negatively biasing the word lines against the P-well includes a step of changing a relative voltage to be biased to the selected word lines, against the P-well, in an order of a pre-charge voltage before a first period, a negative voltage in the first period, the pass voltage Vpass in the second period, and the program voltage or the pass voltage Vpass in the third period.

32. The method as claimed in claim 9,

wherein the step of negatively biasing the word lines against the P-well includes a step of changing a relative voltage to be biased to the selected word lines, against the P-well, in an order of a negative voltage, and then, the program voltage or the pass voltage Vpass.

33. A NAND flash memory device comprising:

a memory cell array formed on a P-well of a semiconductor substrate, the memory cell array including a plurality of cell strings connected to word lines and being divided into a plurality of blocks, each block corresponding to respective word lines selected from the word lines;

means for applying a program voltage to at least one selected word line in a selected block while applying a pass voltage Vpass to deselected word lines; and

means for reducing channel electrons in the cell strings before applying the program voltage.

34. The NAND flash memory device as claimed in claim 33,

wherein the means for reducing the channel electrons applies a negative voltage to the word lines in the selected block.

35. The NAND flash memory device as claimed in claim 33,

wherein the means for applying the program voltage includes a row decoder,

wherein the row decoder comprises:

a block decoder for decoding an address signal to a select signal for selecting a block;

a level shifter for converting a predetermined voltage into a gate drive voltage in response to the select signal; and

a word line driver for transferring a global word line voltage to the word lines,

wherein each of the level shifter and the word line driver includes N-channel transistors which are formed in a Triple-well of the semiconductor substrate, and

wherein the row decoder generates a negative voltage for reducing the channel electrons.

36. The NAND flash memory device as claimed in claim 35,

wherein the row decoder changes the negative voltage to OV after reducing the channel electrons.

37. The NAND flash memory device as claimed in claim 35,

wherein the row decoder generates a high voltage higher than the negative voltage, and

wherein the high voltage at least upon reducing the channel electrons is set to be lower than a voltage obtained by an equation of the high voltage upon programming minus absolute value of the negative voltage.

38. The NAND flash memory device as claimed in claim 33,

wherein the means for applying the program voltage includes a row decoder,

wherein the row decoder comprises:

a block decoder for decoding an address signal to a select signal for selecting a block;

a level shifter for converting a predetermined voltage into a gate drive voltage in response to the select signal; and

a word line driver for transferring a global word line voltage to the word lines,

wherein the level shifter includes P-channel transistors.

39. The NAND flash memory device as claimed in claim 33,

wherein the means for reducing channel electrons applies a positive voltage to the P-well of the semiconductor substrate.

40. The NAND flash memory device as claimed in claim 39,

wherein the means for reducing channel electrons inputs the positive voltage from an external circuit, and applies the positive voltage to the P-well of the semiconductor substrate.

41. A NAND flash memory device comprising:

a memory cell array formed on a P-well of a semiconductor substrate, the memory cell array including a plurality of cell strings connected to word lines and being divided into a plurality of blocks, each block corresponding to respective word lines selected from the word lines, each block being divided into a plurality of pages each page located along each word line, each page being divided into a plurality of sector corresponding to a predetermined number of memory cells,

reducing means for reducing channel electrons in the cell strings; and

programming means for programming memory cells in a unit of one sector selected from the sectors located within one page after reducing channel electrons.

42. The NAND flash memory device as claimed in claim 41,

wherein the programming means programs the memory cells while dividing the page into sectors having a number of sectors in the page at maximum.

43. The NAND flash memory device as claimed in claim 41,

wherein, when the programming means updates data stored in a first sector of a first page of a first block, the programming means randomly programs updated data onto one or ones of combination as selected from among the following:

(a) a second sector of the first page of the first block;

(b) a sector of a second page of the first block; and

(c) a sector of a page of a second block.

44. A system for a NAND flash memory device comprising:

a NAND flash memory array which performs a step of reducing electrons in channel, source and drain regions of the cell strings before programming a memory cell to be programmed;

a peripheral circuitry which controls the step of reducing in the NAND flash memory array;

a control logic which controls an operation of the peripheral circuitry; and

a NAND controller which includes a buffer memory and manages an interface with an operation system in a unit of one sector of the NAND flash memory array.

45. The system as claimed in claim 44,

wherein the NAND controller controls data of the NAND flash memory array to be randomly programmed therein.

46. The system as claimed in claim 44,

wherein the buffer memory has a size of one sector of the NAND flash memory array.

47. The system as claimed in claim 44,

wherein NOP (Number of Operation for Programming in one page) of NAND flash memory array is equal to or larger than two.

48. The system according to claim 44,

wherein the NAND controller controls update data in a page of the NAND memory array to relocate to the same page without deleting old data.

49. The system according to claim 44,

wherein the NAND controller controls update data in a page of the NAND flash memory array to relocate to the same page, without deleting old data and erase operation within the same block.

50. The system according to claim 44,

wherein the NAND controller controls update data in a sector of a page of the NAND flash memory array to relocate to an empty sector within the same page with saving old data as an invalid data, without erase operation within the same block.