High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization

• US 20110310949A1
• Filed: 08/23/2011
• Published: 12/22/2011
• Est. Priority Date: 01/20/2005
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L., Chen, Fred F., Ho, Andrew, Farjad-Rad, Ramin, Poulton, John W., Donnelly, Kevin S., Leibowitz, Brian
• Granted Patent: US 8,989,249 B2
• Time in Patent Office: Days
• US Class Current: 375/229
• CPC Class Codes: H04L 1/0026 Transmission of channel quality indication
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 25/497 by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 27/01 Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04W 52/20 using error rate
• CPC Class Codes: H04W 52/225 Calculation of statistics, e.g. average, variance
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

Claims

1. A first integrated circuit comprising:

a driver to transmit a digital bit stream to a second integrated circuit over a signal path; and

circuitry to equalize the digital bit stream, the circuitry having at least two taps, each tap driven in response to respective bits of the digital bit stream;

where the first integrated circuit has two equalization modes, including a first mode where two of the taps are used to equalize the digital bit stream to compensate for interference, a first one of the two taps being used to compensate for pre-tap interference, and a second mode where two of the taps are used to equalize the digital bit stream, and where the first one of the two taps is not used to compensate for pre-tap interference.

2. The first integrated circuit of claim 1, where the driver and the circuitry are embodied in a transmitter, where the transmitter accepts an input bit sequence in the form of parallel data and where the transmitter uses the circuitry to transmit the digital bit stream as a serial output signal.

3. The first integrated circuit of claim 1, where the first integrated circuit transmits the digital bit stream as a serial, differential output signal.

4. The first integrated circuit of claim 1, where the first integrated circuit is to receive from the second integrated circuit a measure of signal quality, and is to automatically select the first or the second mode in response to the measure of signal quality.

5. The first integrated circuit of claim 4, where the measure of signal quality includes a least one of a data level, a voltage margin or a bit error rate associated with the bit stream transmitted by the first integrated circuit to the second integrated circuit.

6. The first integrated circuit of claim 5, where a performance monitor of the first integrated circuit is to obtain the measure of signal quality for each mode, is to compare the measures to a threshold, and is to select one of the first or second mode which both meets the threshold and represents a minimum power consumption relative to the other of the first or second mode.

7. The first integrated circuit of claim 4, further comprising a controller, the controller to select one of the first mode and the second mode, and further, to define equalization settings for the second integrated circuit.

8. The first integrated circuit of claim 1, where each tap is coupled to a sub-driver, and where drive current for each of plural sub-drivers is variable.

9. The first integrated circuit of claim 8, where total drive current provided by all sub-drivers remains constant irrespective of variance of drive current for any individual sub-driver.

10. The first integrated circuit of claim 9, where drive current of each of the plural sub-drivers is varied in accordance with a multi-bit power setting.

11. The first integrated circuit of claim 10, where drive current of each of the plural sub-drivers is varied according to a fraction of 1/(2ⁿ).

12. The first integrated circuit of claim 1, where:

the bit stream to be transmitted from the first integrated circuit to the second integrated circuit represents first data;

the first integrated circuit further comprises a receiver to receive second data from the second integrated circuit and a decision feedback equalizer to equalize the second data, the decision feedback equalizer having a receive tap;

in the first mode, a specific post-tap latency and a specific pre-tap latency are used to equalize the first data, the circuitry to use transmit equalization to equalize according to the specific pre-tap latency and the receive tap to equalize the second data according to the specific post-tap latency;

in the second mode, the specific post-tap latency is used by the circuitry to equalize the first data, the specific pre-tap latency is not used to equalize the first data, and the receive tap is not used to equalize the second data; and

in the first mode, one of the taps of the circuitry is used to equalize the first data according to the specific pre-tap latency, and in the second mode, the one of the taps is shifted between pre and post cursor operation used to equalize the first data according to the specific post-tap latency.

13. The first integrated circuit of claim 12, further comprising a linear equalizer to equalize the second data.

14. The first integrated circuit of claim 13, where use of the linear equalizer to equalize the second data is enabled during the first mode, and is disabled during one of the second mode or a third mode.

15. The first integrated circuit of claim 12, where the decision feedback equalizer includes at least one partial response tap and at least one infinite impulse response tap and where, in the second mode, at least one of the partial response tap and the infinite impulse response tap is not used to equalize the second data.

16. A first integrated circuit to transmit a digital bit stream to a second integrated circuit over a signal path, comprising:

a driver; and

means for equalizing the digital bit stream using at least two taps, each tap driven in response to respective bits of the digital bit stream, the equalizing performed according to an equalization mode;

where if the equalization mode is a first equalization mode, two of the taps are used to equalize the digital bit stream to compensate for interference, a first one of the two taps being used to compensate for pre-tap interference, and a second mode where two of the taps are used to equalize the digital bit stream; and

where if the equalization mode is a second equalization mode, the first one of the two taps is not used to compensate for pre-tap interference.

17. A method of transmitting a digital bit stream from a first integrated circuit to a second integrated circuit over a signal path, comprising:

equalizing the digital bit stream using circuitry having at least two taps, each tap driven in response to respective bits of the digital bit stream, the equalizing performed according to an equalization mode;

where if the equalization mode is a first equalization mode, two of the taps are used to equalize the digital bit stream to compensate for interference, a first one of the two taps being used to compensate for pre-tap interference, and a second mode where two of the taps are used to equalize the digital bit stream; and

where if the equalization mode is a second equalization mode, the first one of the two taps is not used to compensate for pre-tap interference.

18. The method of claim 17, where the circuitry is embodied in a transmitter, where the transmitter accepts an input bit sequence in the form of parallel data and where the transmitter uses the circuitry to transmit the digital bit stream as a serial output signal.

19. The method of claim 17, further comprising transmitting the digital bit stream as a serial, differential output signal.

20. The method of claim 17, further comprising receiving from the second integrated circuit a measure of signal quality, and automatically selecting the first or the second mode in response to the measure of signal quality.

21. The method of claim 20, where the measure of signal quality includes a least one of a data level, a voltage margin or a bit error rate associated with the bit stream transmitted by the first integrated circuit to the second integrated circuit.

22. The method of claim 21, further comprising obtaining the measure of signal quality for each mode, comparing the measures to a threshold, and selecting one of the first or second mode which both meets the threshold and represents a minimum power consumption relative to the other of the first or second mode.

23. The method of claim 20, wherein the first integrated circuit is a controller, the controller to select one of the first mode and the second mode, and further, to define equalization settings for the second integrated circuit.

24. The method of claim 17, where each tap is coupled to a sub-driver, the method further comprising defining a variable setting to establish a drive current for each of plural sub-drivers.

25. The method of claim 24, where total drive current provided by all sub-drivers remains constant irrespective of variance of drive current for any individual sub-driver.

26. The method of claim 25, further comprising varying drive current of each of the plural sub-drivers in accordance with a multi-bit power setting.

27. The method of claim 26, where drive current of each of the plural sub-drivers is varied according to a fraction of 1/(2ⁿ).

28. The method of claim 17, where:

the bit stream to be transmitted from the first integrated circuit to the second integrated circuit represents first data, and the first integrated circuit includes a transmitter and a receiver;

in the first mode, using the circuitry to equalize the first data includes using transmit equalization to equalize for the pre-tap interference according to a specific pre-tap latency;

the method further comprises, in the first mode, using a receive equalizer tap to equalize the second data according to a specific post-tap latency;

in the second mode, using the circuitry includes using the circuitry to equalize the first data according to the specific post-tap latency, but not the specific pre-tap latency;

in the second mode, the receive tap is not used to equalize the second data according to the specific post-tap latency; and

in the first mode, one of the taps of the circuitry is used to equalize the first data according to the specific pre-tap latency, and in the second mode, the one of the taps is shifted between pre and post cursor operation to equalize the first data according to the specific post-tap latency.

29. The method of claim 28, where using a receive equalizer includes using a linear equalizer to equalize the second data.

30. The method of claim 29, where using the linear equalizer to equalize the second data includes enabling the linear equalizer during the first mode, and disabling the linear equalizer during one of the second mode or a third mode.

31. The method of claim 28, where the receive equalizer includes at least one partial response tap and at least one infinite impulse response tap and where, in the second mode, at least one of the partial response tap and the infinite impulse response tap is not used to equalize the second data.

32. An integrated circuit comprising a transmitter to transmit a data signal over a communication channel, the transmitter including a pre-cursor tap, a configurable second tap, where the transmitter alternatively configures the second tap as a pre-cursor tap or a post-cursor tap.

33. The integrated circuit of claim 32, further comprising a receiver coupled to the communication channel to receive a second data signal, the receiver including a receive equalizer having a receive post-cursor tap, where the receiver disables the receive post-cursor tap at times when the transmitter configures the second tap as a post-cursor tap.

34. The integrated circuit of claim 33, further comprising a controller to configure the second tap as a post-cursor tap and disable the receive post-cursor tap in a low-power mode.