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High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization

  • US 20110310949A1
  • Filed: 08/23/2011
  • Published: 12/22/2011
  • Est. Priority Date: 01/20/2005
  • Status: Active Grant
First Claim
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1. A first integrated circuit comprising:

  • a driver to transmit a digital bit stream to a second integrated circuit over a signal path; and

    circuitry to equalize the digital bit stream, the circuitry having at least two taps, each tap driven in response to respective bits of the digital bit stream;

    where the first integrated circuit has two equalization modes, including a first mode where two of the taps are used to equalize the digital bit stream to compensate for interference, a first one of the two taps being used to compensate for pre-tap interference, and a second mode where two of the taps are used to equalize the digital bit stream, and where the first one of the two taps is not used to compensate for pre-tap interference.

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