VOLTAGE DETECTION SYSTEM AND CONTROLLING METHOD OF THE SAME

• US 20110313700A1
• Filed: 06/20/2011
• Published: 12/22/2011
• Est. Priority Date: 06/21/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: NAKATSU, Shinichi, ETO, Kimiharu, ISHIHARA, Kuniyasu, SHIMODA, Hirotaka, INDO, Seiya, KOUNO, Kyouhei, YAMAGUCHI, Kazuyo, URAKAWA, Yuusuke
• Granted Patent: US 9,501,113 B2
• Time in Patent Office: Days
• US Class Current: 702/64
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

There is a need to solve a possible system malfunction when a power supply voltage decreases steeply. To solve this problem, a control method is provided for a voltage detection system having an interrupt mode and a reset mode. First and second detection levels are configured. When a power supply voltage is higher than the first detection level, a latch circuit is placed in a first state to enable the interrupt mode. When the power supply voltage becomes lower than or equal to the first detection level, an interrupt signal is generated to change the latch circuit from the first state to a second state and enable the reset mode. A system reset is issued when the power supply voltage becomes lower than or equal to the second detection level in the reset mode.

Claims

1. A control method for a voltage detection system having an interrupt mode capable of allowing a CPU to save system information using an interrupt signal and a reset mode capable of resetting a system using a reset signal, the control method comprising the steps of:

setting a first detection level and a second detection level for a voltage lower than the first detection level;

placing a first latch circuit in a first state when a power supply voltage is higher than the first detection level, and setting the voltage detection system to the interrupt mode;

generating the interrupt signal when the power supply voltage becomes lower than or equal to the first detection level, changing the first latch circuit from the first state to a second state, and consequently setting the voltage detection system to the reset mode; and

generating the reset signal when the power supply voltage becomes lower than or equal to the second detection level in the reset mode.

2. The control method of the voltage detection system according to claim 1,

wherein the second detection level is equivalent to a voltage when the power supply voltage reaches an operating voltage for the CPU.

3. The control method of the voltage detection system according to claim 1, comprising the steps of:

detecting that the power supply voltage reaches the first detection level when the first latch circuit is placed in the first state; and

detecting that the power supply voltage reaches the second detection level when the first latch circuit is placed in the second state.

4. The control method of the voltage detection system according to claim 3, comprising the steps of:

outputting the interrupt signal when the first latch circuit is placed in the first state and the power supply voltage becomes lower than or equal to the first detection level; and

outputting the reset signal when the first latch circuit is placed in the second state and the power supply voltage becomes lower than or equal to the second detection level.

5. The control method of the voltage detection system according to claim 1,

wherein the first latch circuit can change from the second state to the first state in accordance with data transmitted from the CPU when the system information save process is completed.

6. The control method of the voltage detection system according to claim 1,

wherein the voltage detection system further includes a second latch circuit that changes from the first state to the second state when the power supply voltage becomes lower than or equal to the first detection level;

wherein the power supply voltage is detected to become the first detection level when the second latch circuit is placed in the first state; and

wherein the power supply voltage is detected to become the second detection level when the second latch circuit is placed in the second state.

7. The control method of the voltage detection system according to claim 6,

wherein the second latch circuit can change from the second state to the first state in accordance with a reset signal transmitted from the CPU after the system information save process terminates.

8. The control method of the voltage detection system according to claim 1,

wherein the first detection level and the second detection level are changeable in accordance with register setting data from the CPU.

9. A voltage detection system having an interrupt mode capable of allowing a CPU to save system information using an interrupt signal and a reset mode capable of resetting a system using a reset signal, the voltage detection system comprising:

a comparison voltage generation circuit that generates a first detection level voltage and a second detection level voltage lower than the first detection level voltage;

a comparator that compares a power supply voltage with one of the first and second detection level voltages;

a latch circuit that operates on a comparison result from the comparator and is set to a first state corresponding to the power supply voltage higher than the first detection level voltage and is set to a second state corresponding to the power supply voltage lower than or equal to the first detection level voltage; and

a control circuit that outputs the interrupt signal corresponding to the latch circuit set to the first state and the power supply voltage lower than or equal to the first detection level and outputs the reset signal corresponding to the latch circuit set to the second state and the power supply voltage lower than or equal to the second detection level.

10. The voltage detection system according to claim 9,

wherein the second detection level is equivalent to a voltage when the power supply voltage reaches an operating voltage for the CPU.

11. The voltage detection system according to claim 9, further comprising:

a comparison voltage selection circuit,

wherein the comparison voltage selection circuit selects and outputs the first detection level voltage to the comparator corresponding to the first latch circuit set to the first state and selects and outputs the second detection level voltage to the comparator corresponding to the first latch circuit set to the second state.

12. The voltage detection system according to claim 11,

wherein the voltage detection system outputs the interrupt signal corresponding to the first latch circuit set to the first state and the power supply voltage lower than or equal to the first detection level and outputs the reset signal corresponding to the first latch circuit set to the second state and the power supply voltage lower than or equal to the second detection level.

13. The voltage detection system according to claim 9,

wherein the first latch circuit can change from the second state to the first state in accordance with data transmitted from the CPU when the system information save process terminates.

14. The voltage detection system according to claim 9, further comprising:

a comparison voltage selection circuit and a second latch circuit,

wherein the second latch circuit changes from a first state to a second state when the power supply voltage becomes lower than or equal to the first detection level;

wherein the comparison voltage selection circuit selects the first detection level voltage corresponding to the second latch circuit set to the first state and outputs the first detection level voltage to the comparator; and

wherein the comparison voltage selection circuit selects the second detection level voltage corresponding to the second latch circuit set to the second state and outputs the second detection level voltage to the comparator.

15. The voltage detection system according to claim 14,

wherein the second latch circuit can change from the second state to the first state in accordance with a reset signal transmitted from the CPU when the system information save process terminates.

16. The voltage detection system according to claim 9,

wherein the first detection level and the second detection level are changeable in accordance with register setting data from the CPU.