MEMORY SYSTEM, PROGRAM METHOD THEREOF, AND COMPUTING SYSTEM INCLUDING THE SAME

• US 20110314207A1
• Filed: 08/29/2011
• Published: 12/22/2011
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, In-Hwan, Chung, Woon-Jae, Yoon, Song-Ho, Ye, Kyung-Wook, Jang, Jun-Ho
• Granted Patent: US 8,223,544 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where the method includes and the system is configured for determining whether data to be stored in a selected memory cell is an LSB data; and if data to be stored in a selected memory cell is not an LSB data, backing up lower data stored in the selected memory cell to a backup memory block of the multi-bit flash memory device.

Claims

1. A memory system comprising:

a multi-bit flash memory device including a plurality of memory blocks; and

a memory controller configured to control the multi-bit flash memory device,

wherein the memory controller is configured to determine whether there exists lower data belonging to a page offset value on the basis of a start address of data to be programmed in the multi-bit flash memory device; and

when it is determined that there exists lower data belonging to a page offset value on the basis of a start address of data to be programmed in the multi-bit flash memory device, the memory controller is configured to control the multi-bit flash memory device to backup the lower data belonging to a page offset value to a free memory block from the memory blocks.

2. The memory system of claim 1, wherein the memory controller is configured to control the multi-bit flash memory device so that the data to be programmed is programmed in the selected memory block when there exists no lower data belonging to a page offset value on the basis of a start address of data to be programmed.

3. The memory system of claim 1, wherein each of the memory cells is configured to store 2-bit data.

4. The memory system of claim 3, wherein the lower data to be backed up to the backup memory block is LSB data.

5. The memory system of claim 1, wherein each of the memory cells is configured to store M-bit data, where M is an integer of 3 or more.

6. The memory system of claim 5, wherein the lower data to be backed up to the backup memory block is a data bit selected from a group comprising a first data bit to a (M−

1)th data bit.

7. The memory system of claim 1, wherein the memory system is configured to detect whether a power failure occurs with respect to the selected memory block.

8. The memory system of claim 7, wherein the memory controller is configured to control the multi-bit flash memory device so that data backed up to the backup memory block and valid data of the selected memory block are copied to a free memory block when a power failure to the selected memory block is detected.

9. The memory system of claim 1, wherein the multi-bit flash memory device is a NAND flash memory device.

10. The memory system of claim 1, wherein the multi-bit flash memory device and the memory controller constitute an OneNAND™

flash memory device.

11. A memory system comprising:

a multi-bit flash memory device including a plurality of memory blocks; and

a memory controller configured to control the multi-bit flash memory device,

wherein the memory controller is configured to determine, as a start address of data to be programmed, an address obtained by adding an address of the data to be programmed and a page offset value.

12. A memory system comprising:

a multi-bit flash memory device including a plurality of memory blocks; and

a memory controller configured to control the multi-bit flash memory device,

wherein the memory controller is configured to assign at least one page to a free page, wherein data to be programmed in the at least one page is data affecting lower data.

13. A memory system comprising:

a multi-bit flash memory device including a plurality of memory blocks; and

a memory controller configured to control the multi-bit flash memory device,

wherein the memory controller is configured to determine whether data to be stored in the multi-bit flash memory device is meta data; and

wherein when data to be stored in the multi-bit flash memory device is judged to be meta data, the memory controller is configured to determine an address obtained by adding an address of the meta data and a page offset value, as a start address of the meta data.

14. The memory system of claim 13, wherein the memory controller is configured to determine whether there exists lower data belonging to a page offset value on the basis of a start address of data to be programmed in the multi-bit flash memory device when data to be stored in the multi-bit flash memory device is determined not to be meta data.

15. The memory system of claim 14, wherein the memory controller is configured to control the multi-bit flash memory device so that lower data belonging to a page offset value on the basis of a start address of data to be programmed is backed up to a free memory block of the memory blocks when there exists lower data belonging to a page offset value on the basis of a start address of data to be programmed in the multi-bit flash memory device.

16. The memory system of claim 15, wherein the memory controller is configured to control the multi-bit flash memory device so that data to be programmed is programmed in the selected memory block when there exists no lower data belonging to a page offset value on the basis of a start address of data to be programmed.

17. A memory system comprising:

a multi-bit flash memory device including a plurality of memory blocks; and

a memory controller configured to control the multi-bit flash memory device,

wherein the memory controller is configured to determine whether data to be stored in the multi-bit flash memory device is meta data; and

when data to be stored in the multi-bit flash memory device is determined to be meta data, the memory controller is configured to assign at least one page to a free page, wherein data to be programmed in the at least one page is data affecting lower data.

18. The memory system of claim 17, wherein the memory controller is configured to determine whether there exists lower data belonging to a page offset value on the basis of a start address of data to be programmed in the multi-bit flash memory device when data to be stored in the multi-bit flash memory device is determined not to be meta data.

19. The memory system of claim 18, wherein the memory controller is configured to control the multi-bit flash memory device to backup lower data belonging to a page offset value on the basis of a start address of data to be programmed to a free memory block from the memory blocks when there exists lower data belonging to a page offset value on the basis of a start address of data to be programmed.

20. The memory system of claim 19, wherein the memory controller is configured to control the multi-bit flash memory device to program the data to be programmed to a selected memory block when there exists no lower data belonging to a page offset value on the basis of a start address of data to be programmed.