DIGITAL SIGNAL PROCESSING ARCHITECTURE SUPPORTING EFFICIENT CODING OF MEMORY ACCESS INFORMATION
First Claim
1. A digital signal processor, comprising:
- an adjustment value register configured to store an initial adjustment value and a succeeding adjustment value;
an address generator circuit communicatively coupled with the adjustment value register and configured to retrieve an instruction including a memory address value that is greater than N and a further instruction including a further memory address value that is less than or equal to N; and
a memory communicatively coupled with the address generator circuit and including a high bank address space defined by memory locations that are uniquely identified with memory address values greater than N, the address generator circuit being further configured toaccess the high bank address space, using the initial adjustment value and the memory address value, when the adjustment value register is not storing the succeeding adjustment value, andaccess the high bank address space, using the succeeding adjustment value and the further memory address value, when the adjustment value register is storing a succeeding adjustment value.
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Accused Products
Abstract
A digital signal processing architecture supporting efficient coding of memory access information is provided. In an example embodiment, a digital signal processor includes an adjustment value register to store an initial adjustment value and a succeeding adjustment value. The digital signal processor may also include an address generator circuit to retrieve an instruction including a memory address value that is greater than N, and a further instruction including a further memory address value that is less than or equal to N. In addition, the digital signal processor may include a memory, which includes a high bank address space defined by memory locations that are uniquely identified with memory address values greater than N. The address generator circuit may access the high bank address space, using initial adjustment value and the memory address value, or using the succeeding adjustment value and the further memory address value.
62 Citations
22 Claims
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1. A digital signal processor, comprising:
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an adjustment value register configured to store an initial adjustment value and a succeeding adjustment value; an address generator circuit communicatively coupled with the adjustment value register and configured to retrieve an instruction including a memory address value that is greater than N and a further instruction including a further memory address value that is less than or equal to N; and a memory communicatively coupled with the address generator circuit and including a high bank address space defined by memory locations that are uniquely identified with memory address values greater than N, the address generator circuit being further configured to access the high bank address space, using the initial adjustment value and the memory address value, when the adjustment value register is not storing the succeeding adjustment value, and access the high bank address space, using the succeeding adjustment value and the further memory address value, when the adjustment value register is storing a succeeding adjustment value. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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setting an initial adjustment value; in an absence of a setting of a succeeding adjustment value, utilizing the initial adjustment value and a first storage location value that is greater than N to access a section of a storage; and in a presence of the setting of the succeeding adjustment value, utilizing the succeeding adjustment value and a second storage location value that is less than or equal to N to access the section of the storage, the section of the storage being defined by, and accessible with, unique storage location values that are greater than N and not less than or equal to N. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A networked digital media system comprising:
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an input/output module configured to receive digital media input via a network and output digital media to a user; a random access memory (RAM) having a high bank address space defined by memory locations uniquely identified with memory address values greater than N; and a digital signal processor communicatively coupled to the RAM and including, an adjustment value register configured to store an initial adjustment value and a succeeding adjustment value, an address generator circuit communicatively coupled with the adjustment value register and being configured to retrieve an instruction including a RAM address value that is greater than N, and a further instruction including a further RAM address value that is less than or equal to N, and the address generator circuit being further configured to access the high bank address space, using the initial adjustment value and the RAM address value, when the adjustment value register is not storing the succeeding adjustment value, and access the high bank address space, using the succeeding adjustment value and the further RAM address value, when the adjustment value register is storing a succeeding adjustment value. - View Dependent Claims (19, 20, 21)
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22. A method comprising:
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requesting that a specific adjustment value be set in a processor register; instructing a processor to access a high bank of memory using a low bank memory address that is less than or equal to N; and confirming that the processor has accessed the high bank of memory at a high bank address, the high bank address being based a sum of the specific adjustment value and the low bank memory address, and the high bank of memory being defined by memory addresses that are greater than N and not less than or equal to N.
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Specification