Thin Film Transistor and Method of Manufacturing the Same

• US 20110315980A1
• Filed: 06/21/2011
• Published: 12/29/2011
• Est. Priority Date: 06/23/2010
• Status: Abandoned Application

• Current Assignee: Jusung Engineering Company Limited
• Original Assignee: Jusung Engineering Company Limited
• Inventors: Kim, Jae Ho
• Application Number:
  US13/165,332
• Publication Number:
  US 20110315980A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02581 Transition metal or rare earth elements
• CPC Class Codes: H01L 29/26 including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Provided are a Thin Film Transistor (TFT) and a method of manufacturing the same. The TFT includes a gate electrode; a source electrode and a drain electrode spaced from the gate electrode in a vertical direction and spaced from each other in a horizontal direction; a gate insulation layer disposed between the gate electrode and the source and drain electrodes; and an active layer disposed between the gate insulation layer and the source and drain electrodes. The active layer is formed of a conductive oxide layer and comprises at least two layers having different conductivities according to an impurity doped into the conductive oxide layer.

Claims

1. A thin film transistor (TFT) comprising:

a gate electrode;

a source electrode and a drain electrode spaced from the gate electrode in a vertical direction and spaced from each other in a horizontal direction;

a gate insulation layer between the gate electrode and the source and drain electrodes; and

an active layer between the gate insulation layer and the source and drain electrodes,

wherein the active layer comprises a first conductive oxide layer having a first conductivity and a second conductive oxide layer having a second conductivity different from said first conductivity, said first and second conductivities corresponding to an impurity in the respective conductive oxide layer.

2. The TFT of claim 1, wherein the first conductive oxide layer comprises zinc oxide (ZnO) having a first composition and the second conductive oxide layer comprises zinc oxide (ZnO) having a second composition different from the first composition.

3. The TFT of claim 1, wherein the first conductive oxide layer comprises a front channel region having relatively high conductivity and the second conductive oxide layer comprises at least one of a bulk region and a back channel region having a lower conductivity than the front channel region.

4. The TFT of claim 3, wherein the front channel region comprises a conductive oxide doped with In.

5. The TFT of claim 4, wherein the front channel region comprises the conductive oxide doped with In and either Ga or Hf.

6. The TFT of claim 3, wherein the second conductive oxide layer comprises the bulk region.

7. The TFT of claim 6, wherein the bulk region consists essentially of an undoped metal oxide layer.

8. The TFT of claim 3, wherein the second conductive oxide layer comprises the back channel region.

9. The TFT of claim 8, wherein the back channel region comprises a metal oxide layer doped with Ga, Hf, Sn, or Al.

10. The TFT of claim 3, wherein the front channel region is at a side of the gate electrode and the bulk region or the back channel region is at a side of the source and drain electrodes.

11. The TFT of claim 3, wherein the second conductive oxide layer comprises the bulk region and the back channel region.

12. The TFT of claim 11, wherein:

the front channel region is at a side of the gate electrode;

the back channel region is at a side of the source and drain electrodes; and

the bulk region is between the front channel region and the back channel region.

13. A method of manufacturing a thin film transistor (TFT), comprising:

forming a gate electrode and source and drain electrodes on a substrate, the gate electrode spaced from the source and drain electrodes in a vertical direction;

forming a gate insulation layer on one of (i) the gate electrode and (ii) the source and drain electrodes; and

forming an active layer on one of (i) the gate insulation layer and (ii) the source and drain electrodes,

wherein the active layer comprises a first conductive oxide layer having a first conductivity and a second conductive oxide layer having a second conductivity different from said first conductivity, said first and second conductivities corresponding to an impurity in the respective conductive oxide layer.

14. The method of claim 13, wherein the first conductive oxide layer comprises a front channel region having a relatively high conductivity and a second conductive oxide layer comprising at least one of a bulk region and a back channel region having a lower conductivity than the front channel region.

15. The method of claim 14, wherein the second conductive oxide layer comprises the bulk region and the back channel region.

16. The method of claim 15, wherein the front channel region, the bulk region, and the back channel region are formed in-situ.

17. The method of claim 15, wherein

the front channel region is formed by Atomic Layer Deposition (ALD);

the bulk region is formed by Chemical Vapor Deposition (CVD); and

the back channel region is formed by ALD or CVD.

18. The method of claim 13, wherein forming the gate electrode and source and drain electrodes, forming the gate insulation layer, and forming the active layer comprises (i) forming the gate electrode on the substrate, (ii) forming the gate insulation layer on the gate electrode, (iii) forming the active layer on the gate insulation layer, and (iv) forming the source and drain electrodes on the active layer.

19. The method of claim 13, wherein forming the gate electrode and source and drain electrodes, forming the gate insulation layer, and forming the active layer comprises (i) forming the source and drain electrodes on the substrate, (ii) forming the active layer gate insulation layer on the source and drain electrodes, (iii) forming the gate insulation layer on the active layer, and (iv) forming the gate electrode on the gate insulation layer.

20. The method of claim 13, wherein the first conductive oxide layer comprises ZnO doped with In, and the second conductive oxide layer comprises undoped ZnO or ZnO doped with Ga, Hf, Sn, or Al.