PASSIVATED UPSTANDING NANOSTRUCTURES AND METHODS OF MAKING THE SAME

• US 20110315988A1
• Filed: 05/12/2011
• Published: 12/29/2011
• Est. Priority Date: 10/05/2009
• Status: Active Grant

• Current Assignee: Zena Technologies, Inc.
• Original Assignee: Zena Technologies, Inc.
• Inventors: Yu, Young-June, Wober, Munib
• Granted Patent: US 9,082,673 B2
• Time in Patent Office: Days
• US Class Current: 257/52
• CPC Class Codes: H01L 27/14 including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation radiation-sensitive components structurally associated with one or more electric light sources only H01L31/14; couplings of light guides with optoelectronic elements G02B6/42
• CPC Class Codes: H01L 27/1446 in a repetitive configuration
• CPC Class Codes: H01L 27/1462 Coatings
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 31/02161 for devices characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/02168 the coatings being antireflective or having enhancing optical properties for the solar cells
• CPC Class Codes: H01L 31/022408 for devices characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/02322 comprising luminescent members, e.g. fluorescent sheets upon the device
• CPC Class Codes: H01L 31/028 including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/035227 the quantum structure being quantum wires, or nanorods carbon nanotubes H10K85/211
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 31/1055 the devices comprising amorphous materials of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/107 the potential barrier working in avalanche mode, e.g. avalanche photodiodes
• CPC Class Codes: H01L 31/145 the semiconductor device sensitive to radiation being characterised by at least one potential-jump barrier or surface barrier
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

Described herein is a device comprising: a substrate; one or more of a nanostructure extending essentially perpendicularly from the substrate; wherein the nanostructure comprises a core of a doped semiconductor, an first layer disposed on the core, and a second layer of an opposite type from the core and disposed on the first layer.

Claims

1. A device comprising:

a substrate;

one or more of a nanostructure extending essentially perpendicularly from the substrate;

wherein the nanostructure comprises a core of a doped semiconductor of a first type, a first layer comprising a lightly doped amorphous semiconductor or an intrinsic amorphous semiconductor, and a second layer comprising a heavily doped amorphous semiconductor layer of a second type opposite from the first type, wherein the first layer is disposed on the core and the second layer is disposed on the first layer.

2. The device of claim 1, wherein the first layer is configured to passivate at least a surface of the core.

3. The device of claim 1, wherein the first layer is disposed isotropically over at least an end portion of the core away from the substrate.

4. The device of claim 3, wherein the second layer is disposed isotropically over at least a portion of the first layer.

5. The device of claim 1, wherein the first layer is disposed on an end surface of the core away from the substrate.

6. The device of claim 5, wherein the second layer is disposed on the first layer.

7. The device of claim 6, wherein the first layer and the second layer are coextensive with the core in at least a direction parallel to the substrate.

8. The device of claim 5, wherein sidewalls of the core are at least partially covered by an electrically insulating layer.

9. The device of claim 8, wherein the first layer and the second layer are coextensive with the electrically insulating layer in at least a direction parallel to the substrate.

12. The device of claim 1, wherein the core comprises one or more doped semiconductor material selected from the group consisting of doped silicon, doped germanium, doped III-V group compound semiconductor, doped II-VI group compound semiconductor, and doped quaternary semiconductor;

wherein the first layer comprises one or more intrinsic amorphous semiconductor material selected from the group consisting intrinsic amorphous silicon, intrinsic amorphous germanium, intrinsic amorphous III-V group compound semiconductor and intrinsic amorphous II-VI group compound semiconductor; and

wherein the second layer comprises one or more heavily doped amorphous semiconductor material selected from the group consisting heavily doped amorphous silicon, heavily doped amorphous germanium, heavily doped amorphous III-V group compound semiconductor and heavily doped amorphous II-VI group compound semiconductor.

14. The device of claim 1, wherein the core is lightly doped.

17. The device of claim 1, wherein the first layer has a thickness of about 2 nm to about 100 nm.

19. The device of claim 1, wherein the second layer has a thickness of at least about 10 nm.

20. The device of claim 1, wherein the second layer, the first layer and the core form a p-i-n junction.

22. The device of claim 1, wherein the nanostructure is a nanowire or a nanoslab.

23. A method of manufacturing the device of claim 1, comprising depositing the first layer on the core by atomic layer deposition (ALD) or chemical vapor deposition (CVD);

and depositing the second layer on the first layer by ALD or CVD.

10. (canceled)

11. (canceled)

13. (canceled)

15. (canceled)

16. (canceled)

18. (canceled)

21. (canceled)

24-176. -176. (canceled)

177. A device comprising:

a substrate;

one or more of a nanostructure extending essentially perpendicularly from the substrate;

wherein the nanostructure comprises a core and a passivation layer, the passivation layer configured to passivate at least a surface of the core and configured to form a p-i-n junction with the core.

178. The device of claim 177, wherein the passivation layer comprises an amorphous material.

179. A device comprising:

a substrate;

one or more of a nanostructure extending essentially perpendicularly from the substrate;

wherein the nanostructure comprises a core and a passivation layer, the passivation layer configured to passivate at least a surface of the core;

wherein the device is configured to convert light to electricity.

180. The device of claim 179, wherein the passivation layer is configured to form a p-i-n junction with the core and the p-i-n junction is functional to convert light to electricity.

181. (canceled)