THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD
First Claim
Patent Images
1. A method comprising:
- forming a channel in a first type semiconductor portion to form a “
U”
shaped portion;
forming a dielectric material within the channel;
forming a control line over the dielectric material;
implanting a second type dopant into both top portions of the “
U”
shaped portion to form a pair of implanted regions; and
forming an upper first type semiconductor portion over one of the implanted regions.
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Accused Products
Abstract
Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
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Citations
37 Claims
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1. A method comprising:
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forming a channel in a first type semiconductor portion to form a “
U”
shaped portion;forming a dielectric material within the channel; forming a control line over the dielectric material; implanting a second type dopant into both top portions of the “
U”
shaped portion to form a pair of implanted regions; andforming an upper first type semiconductor portion over one of the implanted regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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forming a conductor region beneath a first type semiconductor portion separated therefrom by a dielectric material; forming a channel in the first type semiconductor portion to form a “
U”
shaped portion;forming a dielectric material within the channel; forming a control line over the dielectric material; implanting a second type dopant into both top portions of the “
U”
shaped portion to form a pair implanted regions; andforming an upper first type semiconductor portion over one of the implanted regions. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method comprising:
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forming two vertically coupled P-N junctions on a first substrate; forming a conductor region over the two vertically coupled P-N junctions; flipping the first substrate, and bonding the conductor region to a dielectric material of a second substrate; forming a third vertically coupled P-N junction on a back side of a portion of the first substrate; forming a control line between two of the vertically coupled P-N junctions; forming a buried transmission line from a portion of the conductor region; and forming a second transmission line on top of the third vertically coupled P-N junction. - View Dependent Claims (17, 18, 19, 20)
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21. A method comprising:
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forming a vertical stack of alternating conductivity type semiconductor material, including; forming two vertically coupled P-N junctions on a first substrate; forming a conductor region over the two vertically coupled P-N junctions; flipping the first substrate, and bonding the conductor region to a dielectric material of a second substrate; forming a third vertically coupled P-N junction on a back side of a portion of the first substrate; forming trenches in the vertical stack to form an array of vertical pillars of alternating conductivity type semiconductor material; and forming at least one control line in a trench between two adjacent pillars separated from a channel region by a dielectric material. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29)
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30. A semiconductor memory device, comprising:
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an array of memory cells, each memory cell including a folded first conductivity type semiconductor region, each folded region having two upward facing ends; a pair of second conductivity type semiconductor regions coupled to the upward facing ends; a control line within the folded region between the two upward facing ends; a first conductivity type semiconductor cap on one of the second conductivity type semiconductor regions; and a first transmission line coupled to the other second conductivity type semiconductor region. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37)
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Specification