SEMICONDUCTOR DEVICE

• US 20110316062A1
• Filed: 06/02/2011
• Published: 12/29/2011
• Est. Priority Date: 06/29/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KONDO, Masao, MORIKAWA, Masatoshi, GOTO, Satoshi
• Granted Patent: US 8,786,002 B2
• Time in Patent Office: Days
• US Class Current: 257/312
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.

Claims

1. A semiconductor device, comprising:

an antenna switch having a transmission terminal, an antenna terminal, and a reception terminal,

wherein the antenna switch is a semiconductor device having;

(a) a plurality of first field effect transistors coupled in series between the transmission terminal and the antenna terminal; and

(b) a plurality of second field effect transistors coupled in series between the reception terminal and the antenna terminal, and

wherein, between a source region and a drain region of each of the second field effect transistors coupled in series, a capacitance circuit is coupled which has a voltage dependency such that, in either of cases where a positive voltage is applied to the drain region based on a potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, a capacitance decreases to a value smaller than that in a state where the potential of the source region and a potential of the drain region are at the same level.

2. The semiconductor device according to claim 1,

wherein the capacitance circuit comprises a first MOS diode capacitance element and a second MOS diode capacitance element which are formed over a SOI substrate including a support substrate, a buried insulating layer formed over the support substrate, and a semiconductor layer formed over the buried insulating layer,

wherein the first MOS diode capacitance element has:

(c1) a first semiconductor region of a first conductivity type formed in the semiconductor layer;

(c2) a first capacitance insulating film formed over the first semiconductor region; and

(c3) a first electrode formed over the first capacitance insulating film,

wherein the second MOS diode capacitance element has;

(d1) a second semiconductor region of the first conductivity type formed in the semiconductor layer;

(d2) a second capacitance insulating film formed over the second semiconductor region; and

(d3) a second electrode formed over the second capacitance insulating film, and

wherein the capacitance circuit includes a first terminal electrically coupled to the first semiconductor region of the first MOS diode capacitance element, and a second terminal electrically coupled to the second semiconductor region of the second MOS diode capacitance element, and has a configuration in which the first electrode of the first MOS diode capacitance element is electrically coupled to the second electrode of the second MOS diode capacitance element.

3. The semiconductor device according to claim 2,

wherein the capacitance circuit further has a first resistance element provided between the first terminal and the first electrode, and a second resistance element provided between the second terminal and the second electrode, and

wherein a resistance value of the first resistance element is the same as a resistance value of the second resistance element.

4. The semiconductor device according to claim 1,

wherein the capacitance circuit comprises a first MOS diode capacitance element and a second. MOS diode capacitance element which are formed over a SOI substrate including a support substrate, a buried insulating layer formed over the support substrate, and a semiconductor layer formed over the buried insulating layer,

wherein the first MOS diode capacitance element has:

(c1) a first semiconductor region of a first conductivity type formed in the semiconductor layer;

(c2) a first capacitance insulating film formed over the first semiconductor region; and

(c3) a first electrode formed over the first capacitance insulating film,

wherein the second MOS diode capacitance element has;

(d1) a second semiconductor region of the first conductivity type formed in the semiconductor layer;

(d2) a second capacitance insulating film formed over the second semiconductor region; and

(d3) a second electrode formed over the second capacitance insulating film, and

wherein the capacitance circuit includes a first terminal electrically coupled to the first electrode of the first MOS diode capacitance element, and a second terminal electrically coupled to the second electrode of the second MOS diode capacitance element, and has a configuration in which the first semiconductor region of the first MOS diode capacitance element is electrically coupled to the second semiconductor region of the second MOS diode capacitance element.

5. The semiconductor device according to claim 4,

wherein the first semiconductor region and the second semiconductor region are formed integrally in the semiconductor region.

6. The semiconductor device according to claim 5,

wherein the capacitance circuit further has a first resistance element provided between the first terminal and the first semiconductor region, and a second resistance element provided between the second terminal and the second semiconductor region, and

wherein a resistance value of the first resistance element is the same as a resistance value of the second resistance element.

7. The semiconductor device according to claim 1,

wherein the capacitance circuit comprises a first MOS diode capacitance element and a second MOS diode capacitance element which are formed over a SOI substrate including a support substrate, a buried insulating layer formed over the support substrate, and a semiconductor layer formed over the buried insulating layer,

wherein the first MOS diode capacitance element has:

(c1) a first semiconductor region of a first conductivity type formed in the semiconductor layer;

(c2) a first capacitance insulating film formed over the first semiconductor region; and

(c3) a first electrode formed over the first capacitance insulating film,

wherein the second MOS diode capacitance element has;

(d1) a second semiconductor region of the first conductivity type formed in the semiconductor layer;

(d2) a second capacitance insulating film formed over the second semiconductor region; and

(d3) a second electrode formed over the second capacitance insulating film, and

wherein the capacitance circuit includes a first terminal electrically coupled to the first semiconductor region of the first MOS diode capacitance element, and a second terminal electrically coupled to the second semiconductor region of the second MOS diode capacitance element, and has a configuration in which the first semiconductor region of the first MOS diode capacitance element is electrically coupled to the second electrode of the second MOS diode capacitance element, and the first electrode of the first MOS diode capacitance element is electrically coupled to the second semiconductor region of the second MOS diode capacitance element.

8. The semiconductor device according to claim 7,

wherein the capacitance circuit further has a resistance element provided between the first terminal and the second terminal.

17. The semiconductor device according to claim 1,

wherein the first field effect transistors and the second field effect transistors are formed over a SOI substrate including a support substrate, a buried insulating layer formed over the support substrate, and a semiconductor layer formed over the buried insulating layer.

19. The semiconductor device according to claim 1,

wherein, between a source region and a drain region of each of the first field effect transistors coupled in series also, the capacitance circuit is coupled.

9. A semiconductor device, comprising:

an antenna switch having a transmission terminal, an antenna terminal, and a reception terminal,

wherein the antenna switch is a semiconductor device having;

(a) a plurality of first field effect transistors coupled in series between the transmission terminal and the antenna terminal; and

(b) a plurality of second field effect transistors coupled in series between the reception terminal and the antenna terminal, and

wherein, between a first coupling terminal and a second coupling terminal which are between the second field effect transistors, a capacitance circuit is coupled which has a voltage dependency such that, in either of cases where a positive voltage is applied to the second coupling terminal based on a potential of the first coupling terminal and where a negative voltage is applied to the second coupling terminal based on the potential of the first coupling terminal, a capacitance decreases to a value smaller than that in a state where the potential of the first coupling terminal and a potential of the second coupling terminal are at the same level.

10. The semiconductor device according to claim 9,

wherein the capacitance circuit comprises a first MOS diode capacitance element and a second MOS diode capacitance element which are formed over a SOI substrate including a support substrate, a buried insulating layer formed over the support substrate, and a semiconductor layer formed over the buried insulating layer,

wherein the first MOS diode capacitance element has:

(c1) a first semiconductor region of a first conductivity type formed in the semiconductor layer;

(c2) a first capacitance insulating film formed over the first semiconductor region; and

(c3) a first electrode formed over the first capacitance insulating film,

wherein the second MOS diode capacitance element has;

(d1) a second semiconductor region of the first conductivity type formed in the semiconductor layer;

(d2) a second capacitance insulating film formed over the second semiconductor region; and

(d3) a second electrode formed over the second capacitance insulating film, and

wherein the capacitance circuit includes a first terminal electrically coupled to the first semiconductor region of the first MOS diode capacitance element, and a second terminal electrically coupled to the second semiconductor region of the second MOS diode capacitance element, and has a configuration in which the first electrode of the first MOS diode capacitance element is electrically coupled to the second electrode of the second MOS diode capacitance element.

11. The semiconductor device according to claim 10,

wherein the capacitance circuit further has a first resistance element provided between the first terminal and the first electrode, and a second resistance element provided between the second terminal and the second electrode, and

wherein a resistance value of the first resistance element is the same as a resistance value of the second resistance element.

12. The semiconductor device according to claim 9,

wherein the capacitance circuit comprises a first MOS diode capacitance element and a second MOS diode capacitance element which are formed over a SOI substrate including a support substrate, a buried insulating layer formed over the support substrate, and a semiconductor layer formed over the buried insulating layer,

wherein the first MOS diode capacitance element has:

(c1) a first semiconductor region of a first conductivity type formed in the semiconductor layer;

(c2) a first capacitance insulating film formed over the first semiconductor region; and

(c3) a first electrode formed over the first capacitance insulating film,

wherein the second MOS diode capacitance element has;

(d1) a second semiconductor region of the first conductivity type formed in the semiconductor layer;

(d2) a second capacitance insulating film formed over the second semiconductor region; and

(d3) a second electrode formed over the second capacitance insulating film, and

wherein the capacitance circuit includes a first terminal electrically coupled to the first electrode of the first MOS diode capacitance element, and a second terminal electrically coupled to the second electrode of the second MOS diode capacitance element, and has a configuration in which the first semiconductor region of the first MOS diode capacitance element is electrically coupled to the second semiconductor region of the second MOS diode capacitance element.

13. The semiconductor device according to claim 12,

wherein the first semiconductor region and the second semiconductor region are formed integrally in the semiconductor region.

14. The semiconductor device according to claim 13,

wherein the capacitance circuit further has a first resistance element provided between the first terminal and the first semiconductor region, and a second resistance element provided between the second terminal and the second semiconductor region, and

wherein a resistance value of the first resistance element is the same as a resistance value of the second resistance element.

15. The semiconductor device according to claim 9,

wherein the capacitance circuit comprises a first MOS diode capacitance element and a second MOS diode capacitance element which are formed over a SOI substrate including a support substrate, a buried insulating layer formed over the support substrate, and a semiconductor layer formed over the buried insulating layer,

wherein the first MOS diode capacitance element has:

(c1) a first semiconductor region of a first conductivity type formed in the semiconductor layer;

(c2) a first capacitance insulating film formed over the first semiconductor region; and

(c3) a first electrode formed over the first capacitance insulating film,

wherein the second MOS diode capacitance element has;

(d1) a second semiconductor region of the first conductivity type formed in the semiconductor layer;

(d2) a second capacitance insulating film formed over the second semiconductor region; and

(d3) a second electrode formed over the second capacitance insulating film, and

wherein the capacitance circuit includes a first terminal electrically coupled to the first semiconductor region of the first MOS diode capacitance element, and a second terminal electrically coupled to the second semiconductor region of the second MOS diode capacitance element, and has a configuration in which the first semiconductor region of the first MOS diode capacitance element is electrically coupled to the second electrode of the second MOS diode capacitance element, and the first electrode of the first MOS diode capacitance element is electrically coupled to the second semiconductor region of the second MOS diode capacitance element.

16. The semiconductor device according to claim 15,

wherein the capacitance circuit further has a resistance element provided between the first terminal and the second terminal.

18. The semiconductor device according to claim 9,

wherein the first field effect transistors and the second field effect transistors are formed over a SOI substrate including a support substrate, a buried insulating layer formed over the support substrate, and a semiconductor layer formed over the buried insulating layer.

20. The semiconductor device according to claim 9,

wherein, between a third coupling terminal and a fourth coupling terminal between the first field effect transistors also, the capacitance circuit is coupled which has a voltage dependency such that, in either of cases where a positive voltage is applied to the fourth coupling terminal based on a potential of the third coupling terminal and where a negative voltage is applied to the fourth coupling terminal based on the potential of the third coupling terminal, the capacitance decreases to a value smaller than that in a state where the potential of the third coupling terminal and a potential of the fourth coupling terminal are at the same level.