TRENCH MOSFET WITH TRENCHED FLOATING GATES HAVING THICK TRENCH BOTTOM OXIDE AS TERMINATION

• US 20110316075A1
• Filed: 06/29/2011
• Published: 12/29/2011
• Est. Priority Date: 11/20/2009
• Status: Active Grant

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: HSIEH, Fu-Yuan
• Granted Patent: US 8,525,255 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells

Abstract

A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask.

Claims

1. A semiconductor power device comprising:

a plurality of power transistor cells disposed in an active area near a top surface of an epitaxial layer of first conductivity type grown on a semiconductor substrate of said first conductivity type wherein each of said transistor cells is surrounded by trenched gates;

multiple trenched floating gates disposed in a termination area surrounding said active area and each of said trenched floating gates having a floating voltage wherein said trenched floating gates further penetrating through a body region and extending into said epitaxial layer;

said trenched gates and said multiple trenched floating gates comprising a conductive material padded by a gate insulation layer filled in trenches, wherein said gate insulation layer having a thick bottom oxide on bottom surface of said trenches with a thickness greater than sidewall oxide along sidewall of said trenches;

said body region of a second conductivity type formed in both said active cell area and said termination area disposed immediately adjacent to said trenched floating gates;

said trenched gates further extended to wider trenched gates in a gate contact area having a greater trench width than said trench gates in said active cell area for electrically connecting to a gate metal; and

a source region of said first conductivity type disposed only in said power transistor cells in said active area but not in said termination area comprising said multiple trenched floating gates and no source regions disposed in said epitaxial layer regions adjacent to said wider trenched gate in said gate contact area

2. The semiconductor power device of claim 1 wherein said trenches have rounded bottom.

3. The semiconductor power device of claim 1 wherein said thick bottom oxide comprising a HDP oxide surrounded by a thermally grown pad oxide layer on bottom surface of said trenches.

4. The semiconductor power device of claim 1 wherein:

said thick bottom oxide in conjunction with said sidewall oxide forms a U shape interface with said conductive material in said trenches.

5. The semiconductor power device of claim 1 wherein:

said thick bottom oxide in conjunction with said sidewall oxide forms a W shape interface with said conductive material in said trenches.

6. The semiconductor power device of claim 1 wherein said

trenched floating gates in said termination area have trench width wider than said trenched gates in said active area.

7. The semiconductor power device of claim 1 wherein said source

region has doping concentration along channel region same as along trenched source-body contact region at same distance from the surface of said epitaxial layer, and source junction depth is same as along said channel region than along said trenched source-body contact.

8. The semiconductor power device of claim 1 wherein said source

region has doping concentration along channel region lower than along trenched source-body contact region at same distance from the surface of said epitaxial layer, and source junction depth is shallower along said channel region than along said trenched source-body contact, and the doping profile of said source region along the surface of said epitaxial layer has Gaussian-distribution from said trenched source-body contact to said channel region.

9. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising N-channel MOSFET cells and said source region further comprising N+ doped source region disposed only in said active area but not in said termination area comprising said multiple trenched floating gates filled with an N+ doped polysilicon layer padded with said gate insulation layer and no N+ doped source regions disposed in said epitaxial layer adjacent to said wider trenched gate in said gate contact area.

10. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising P-channel MOSFET cells and said source region further comprising P+ doped source region disposed only in said active area but not in said termination area comprising said multiple trenched floating gates filled with a P+ doped polysilicon layer padded with said gate insulation layer and no P+ doped source regions disposed in said epitaxial layer adjacent to said wider trenched gate in said gate contact area.

11. The semiconductor power device of claim 1 further comprising:

an insulation layer overlying said semiconductor device and a plurality of trenched source-body contacts opened through said insulation layer and said source region and extending into said body region for filling with a source-body contact metal plug therein for electrically contacting said source region and said body region; and

a plurality of trenched gate contacts opened through said insulating layer and extending into said wider trenched gates wider than said trench gates in said active cell area for filling with a gate-contact metal plug therein for electrically contacting said wider trenched gate disposed in said epitaxial layer having no source regions adjacent to said wider trenched gate.

12. The semiconductor power device of claim 11 further comprising:

a patterned source metal and a patterned gate metal disposed on top of said insulating layer for electrically contacting said source-body contact metal plug and said gate-contact metal plugs respectively.

13. The semiconductor power device of claim 1 wherein:

said multiple trenched floating gates in said termination comprising at least three trenched gates.

14. The semiconductor power device of claim 1 wherein:

said multiple trenched floating gates in said termination having equal space between one another.

15. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising N-channel MOSFET cells disposed near the top surface of said epitaxial layer supported on a red phosphorous substrate.

16. The semiconductor power device of claim 1 further comprising

a drain electrode disposed on a bottom surface of said semiconductor substrate supporting said semiconductor power device with said trenched gates and said source region disposed near the top surface of said epitaxial layer.

17. The semiconductor power device of claim 1 further comprises an on-resistance reduction doped region of first type conductivity wrapping around said trenched gate bottom and connecting to said body region, having a doping concentration higher than said epitaxial layer;

18. A semiconductor power device comprising:

a plurality of N-channel or P-channel MOSFET cells surrounded by trenched gates in an active area near a top surface of an epitaxial layer of first conductivity grown on a substrate of first conductivity type;

said trenched gates further extended to wider trenched gates in a gate contact area having greater trench width than said trench gates in said active cell area for electrically connecting a gate metal;

at least three trenched floating gates disposed in a termination area surrounding said active cell area having a floating voltage wherein said trenched floating gates penetrating through a body region and extending into said epitaxial layer;

said trenched gates and said trenched floating gates comprising a conductive material padded by a gate insulation layer filled in trenches, wherein said gate insulation layer having a thick bottom oxide on bottom surface of said trenches with a thickness greater than sidewall oxide along sidewall of said trenches;

said body region formed in both said active cell area and said termination area disposed immediately adjacent to said trenched floating gates;

a source region of said first conductivity type disposed only in said active area but not in said termination area having said multiple trenched floating gates and no source regions disposed in said epitaxial layer adjacent to said wider trenched gate in said gate contact area

an insulation layer overlying said semiconductor device and a plurality of source-body contact trenches opened through said insulation layer and said source region and extending into said body region for filling with a source-body contact metal plug therein for electrically contacting said source region and said body region;

a patterned source metal layer disposed on top of said insulating layer for electrically contacting said source-body contact plug; and

a drain electrode disposed on a bottom surface of a semiconductor substrate supporting said semiconductor power device.

19. The semiconductor power device of claim 18 wherein:

said N-channel MOSFET cells are disposed near top surface of said epitaxial layer supported on a red phosphorous substrate and P-channel MOSFET cells are disposed near top surface of said epitaxial layer supported on a boron substrate.

20. A method of manufacturing a semiconductor power device comprising:

(a) forming a plurality of trenches in an epitaxial layer of first conductivity type;

(b) depositing a HDP oxide on trench sidewall, and bottom, and top surface of said mesa area wherein said trench sidewall has thinner oxide than said trench bottom and said mesa area;

(d) removing, using wet etching, the oxide on trench sidewall completely, and the oxide on trench bottom and said mesa area partially wherein a remaining oxide and said pad oxide on trench bottom defined as bottom oxide layer;

(e) depositing a photo resist filled into said trenches and top surface of said mesa area;

(f) removing a portion of said photo resist from top surface of said mesa area to expose said portion of surface area of said oxide on said mesa area where said oxide layer can be removed;

(g) removing said oxide on said top surface of said mesa area completely;

(h) forming a gate oxide on trench sidewall; and

(i) forming trenched gates, trenched floating gates, body regions, source regions and trenched source-body contact in said epitaxial layer.

21. The method according to claim 20, wherein the step (b) further comprises forming a pad layer on trench sidewall and bottom, and top surface of a mesa area between adjacent trenches before depositing said HDP oxide.

22. The method according to claim 20, wherein the step (0 is performed by blankly exposing said photo resist without having an additional mask.

23. The method according to claim 20, wherein the step (f) is performed by blankly dry asking said photo resist without having an additional mask.

24. The method according to claim 20, wherein the step (f) is performed by exposing photo resist with an additional oversized mask protecting said photo resist on top of said trenches.

25. The method according to claim 20, wherein the step (i) further comprises:

applying a contact mask and dry oxide etching to remove an insulation layer overlying said semiconductor device from contact open areas;

implanting a dopant of said first conductivity type through said contact open areas and diffusing it to form said source regions; and

then forming trenched source-body contact into body region by dry silicon etch through said source regions.