MOS TRANSISTOR, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE

• US 20110316087A1
• Filed: 03/30/2011
• Published: 12/29/2011
• Est. Priority Date: 06/23/2010
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Pidin, Sergey
• Granted Patent: US 8,395,222 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode. The accumulated stress is the tensile stress if the conductivity type is an n-type, and is a compressive stress if the conductivity type is a p-type.

Claims

1. A MOS transistor, comprising:

a silicon substrate in which a device region is defined by a device isolation region;

a gate electrode formed over the silicon substrate in the device region and providing a channel region in the silicon substrate;

a source extension region and a drain extension region formed in the silicon substrate on a first side of the channel region and a second side of the channel region, respectively, in the device region, the source extension region and the drain extension region being of a first conductivity type corresponding to one of an n-type and a p-type;

a first conductivity-type source region formed in the silicon substrate on said first side of the channel region in the device region so as to be apart from the channel region and overlap a part of the source extension region;

a first conductivity-type drain region formed in the silicon substrate on said second side of the channel region in the device region so as to be apart from the channel region and overlap a part of the drain extension region;

a first stress layer formed over the silicon substrate in the device region so as to cover the source region and extend from the device isolation region toward the channel region on said first side of the channel region, the first stress layer accumulating a first stress corresponding to one of a tensile stress and a compressive stress; and

a second stress layer formed over the silicon substrate in the device region so as to cover the drain region and extend from the device isolation region toward the channel region on said second side of the channel region, the second stress layer accumulating said first stress,

said first stress layer having a first extending part rising from an end of the first stress layer near the channel region upward from the silicon substrate along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode,

said second stress layer having a second extending part rising from an end of the second stress layer near the channel region upward from the silicon substrate along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode,

said first stress being the tensile stress if the first conductivity type is the n-type, and said first stress being the compressive stress if the first conductivity type is the p-type.

2. The MOS transistor according to claim 1, wherein a first gap is provided between the first sidewall of the gate electrode and the first extending part of the first stress layer, and a second gap is provided between the second sidewall of the gate electrode and the second extending part of the second stress layer.

3. The MOS transistor according to claim 2, wherein a gap size of each of the first gap and the second gap in a direction of a channel length decreases from a bottom near the silicon substrate toward a top away from the silicon substrate.

4. The MOS transistor according to claim 2, wherein a first residual of a first offset sidewall spacer provided to the first sidewall of the gate electrode remains at a bottom of the first gap, and a second residual of a second offset sidewall spacer provided to the second sidewall of the gate electrode remains at a bottom of the second gap, and

a height of the first and second residuals from a surface of the silicon substrate is at or below 40% of a height of the gate electrode.

5. The MOS transistor according to claim 2, further comprising:

a stressless interlayer dielectric film covering the gate electrode and the first and second stress layers,

wherein the first gap and the second gap are located under the interlayer dielectric film.

6. The MOS transistor according to claim 5, wherein the interlayer dielectric film covers the gate electrode and the first and second stress layers using an insulating layer with a uniform thickness, and

the first gap and the second gap are located under the insulating layer.

7. The MOS transistor according to claim 1, wherein a space between the first sidewall of the gate electrode and the first extending part of the first stress layer and a space between the second sidewall of the gate electrode and the second extending part of the second stress layer are filled with a stressless layer that does not accumulate a stress therein.

8. A semiconductor device comprising:

a silicon substrate in which a first device region and a second device region are defined by a device isolation region;

an n-channel MOS transistor formed in the first device region; and

a p-channel MOS transistor formed in the second device region,

the n-channel MOS transistor including;

a first gate electrode formed over the silicon substrate in the first device region and providing a first channel region in the silicon substrate;

an n-type source extension region and an n-type drain extension region formed in the silicon substrate on a first side and a second side of the first channel region, respectively, in the first device region;

an n-type source region formed in the silicon substrate on said first side of the first channel region in the first device region so as to be apart from the first channel region and overlap a part of the n-type source extension region;

an n-type drain region formed in the silicon substrate on said second side of the first channel region in the first device region so as to be apart from the first channel region and overlap a part of the n-type drain extension region;

a first tensile stress layer formed over the silicon substrate in the first device region so as to cover the n-type source region and extend from the device isolation region toward the first channel region on said first side of the first channel region; and

a second tensile stress layer formed over the silicon substrate in the first device region so as to cover the n-type drain region and extend from the device isolation region toward the first channel region on said second side of the first channel region,

said first tensile stress layer having a first extending part rising from an end of the first tensile stress layer near the first channel region upward from the silicon substrate along a first sidewall of the first gate electrode but separated from the first sidewall of the first gate electrode on said first side of the first channel region, and

said second tensile stress layer having a second extending part rising from an end of the second tensile stress layer near the channel region upward from the silicon substrate along a second sidewall of the first gate electrode but separated from the second sidewall of the first gate electrode on said second side of the first channel region,.

the p-channel MOS transistor including;

a second gate electrode formed over the silicon substrate in the second device region and providing a second channel region in the silicon substrate;

a p-type source extension region and a p-type drain extension region formed in the silicon substrate on a first side and a second side of the second channel region, respectively, in the second device region;

a p-type source region formed in the silicon substrate on said first side of the second channel region in the second device region so as to be apart from the second channel region and overlap a part of the p-type source extension region;

a p-type drain region formed in the silicon substrate on said second side of the second channel region in the second device region so as to be apart from the second channel region and overlap a part of the p-type drain extension region;

a first compressive stress layer formed over the silicon substrate in the second device region so as to cover the p-type source region and extend from the device isolation region toward the second channel region on said first side of the second channel region; and

a second compressive stress layer formed over the silicon substrate in the second device region so as to cover the p-type drain region and extend from the device isolation region toward the second channel region on said second side of the second channel region,

said first compressive stress layer having a third extending part rising from an end of the first compressive stress layer near the second channel region upward from the silicon substrate along a first sidewall of the second gate electrode but separated from the first sidewall of the second gate electrode on said first side of the second channel region, and

said second compressive stress layer having a fourth extending part rising from an end of the second compressive stress layer near the second channel region upward from the silicon substrate along a second sidewall of the second gate electrode but separated from the second sidewall of the second gate electrode on said second side of the second channel region.

9. A method of manufacturing a MOS transistor, comprising:

forming a gate electrode over a silicon substrate in a device region defined by a device isolation region in the silicon substrate;

ion-implanting first conductivity-type impurities in the silicon substrate in the device region to form a first conductivity-type source extension region and a first conductivity-type drain extension region on a first side and a second side of a channel region provided directly below the gate electrode, respectively, the first conductivity-type corresponding to n-type or p-type;

forming a first offset sidewall spacer and a second offset sidewall spacer on a first sidewall and a second sidewall of the gate electrode, respectively, the first sidewall of the gate electrode being located on a first side of the channel region and the second sidewall of the gate electrode being located on a second side of the channel region;

ion-implanting first conductivity-type impurities in the silicon substrate using the gate electrode and the first and second offset sidewall spacers as a mask to form a first conductivity-type source region and a first conductivity-type drain region on the first side and the second side of the channel region, respectively, such that the first conductivity-type source region is apart from the channel region and overlaps a part of the source extension region and that the first-conductivity-type drain region is apart from the channel region and overlaps a part of the drain extension region;

forming a stress layer over the silicon substrate, covering the first offset sidewall spacer, the gate electrode, and the second offset sidewall spacer, the stress layer accumulating a first stress corresponding to one of a tensile stress and a compressive stress;

forming a protection layer over the silicon substrate covering the stress layer;

performing chemical mechanical polishing on the protection layer to expose a part of the stress layer covering the first and second offset sidewall spacers and the gate electrode;

patterning by etching the exposed part of the stress layer to separate the stress layer into a first stress layer located on the first side of the channel region and extending along the first offset sidewall spacer and a second stress layer located on the second side of the channel region and extending along the second offset sidewall spacer, the first stress layer and the second stress layer accumulating the first stress, and to expose top faces of the first and second offset sidewall spacers; and

removing by etching the first and second offset sidewall spacers from the top faces thereof to produce a first gap between the first sidewall of the gate electrode and a first extending part of the first stress layer arising upward from the silicon substrate along the first sidewall of the gate electrode, and a second gap between the second sidewall of the gate electrode and a second extending part of the second stress layer arising upward from the silicon substrate along the second sidewall of the gate electrode,

said first stress being the tensile stress if the first conductivity type is the n-type, and said first stress being the compressive stress if the first conductivity type is the p-type.

10. The manufacturing method according to claim 9, wherein

the removing by etching the first and second offset sidewall spacers from the top faces thereof allows a first residual of the first offset sidewall spacer and a second residual of the second offset sidewall spacer to remain in the first gap and the second gap, respectively, as long as a height of the first residual and a height of the second residual from the silicon substrate are at or less than 40% of a height of the gate electrode.

11. The manufacturing method according to claim 9, wherein each of the first and second offset sidewall spacers has a first width in a direction of a gate length at a bottom contacting the silicon substrate and a second width smaller than the first width, the second width decreasing as the offset sidewall spacer is apart from the silicon substrate.

12. The manufacturing method according to claim 9, wherein the removing by etching the first and second offset sidewall spacers from the top faces thereof etches the protection layer concurrently.

13. The manufacturing method according to claim 9, further comprising:

after producing the first gap and the second gap, forming an interlayer dielectric film over the silicon substrate by a plasma CVD method under a condition so as not to accumulate a substantive stress therein.

14. The manufacturing method according to claim 13, wherein the interlayer dielectric film is formed so as to cover the first gap and the second gap at top of the first extending part of the first stress layer and top of the second extending part of the second stress layer to maintain the first gap and the second gap under the interlayer dielectric film.

15. The manufacturing method according to claim 13, wherein the interlayer dielectric film is formed so as to fill the first gap and the second gap.

16. The manufacturing method according to claim 9, further comprising:

after producing the first gap and the second gap, forming an insulating layer with a uniform thickness over the silicon substrate so as to cover the first gap and the second gap at top of the first extending part of the first stress layer and top of the second extending part of the second stress layer to maintain the first gap and the second gap under the interlayer dielectric film.